24.6.7 Channel n Control
This register allows the user to configure channel n. To write to this register, perform a single 32-bit write of all the configuration data.
| Name: | CHANNEL[n] |
| Offset: | 0x20 + n*0x04 [n=0..3] |
| Reset: | 0x00008000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ONDEMAND | RUNSTDBY | EDGSEL[1:0] | PATH[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – ONDEMAND Generic Clock On Demand
Note: This bit has no effect
when channel n is configured as an asynchronous
path.
| Value | Description |
|---|---|
| 0 | GCLK_EVSYS_CHn is always on if channel n is configured (CHANNEL[n].EVGEN is not 0x00) and the generic clock source is enabled |
| 1 | GCLK_EVSYS_CHn is only on when requested by channel n |
Bit 14 – RUNSTDBY Run in Standby
This bit controls the behavior during Standby sleep mode.
| Value | Description |
|---|---|
| 0 | Channel n is disabled in Standby sleep mode when configured with a synchronous or resynchronized path |
| 1 | Channel n is not stopped in Standby sleep mode and depends on CHANNEL[n].ONDEMAND |
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
This bit field controls the edge detection for channel n.
Note: This bit field must be written to
‘
0’ when channel n is configured with asynchronous
path.| Value | Name | Description |
|---|---|---|
| 0x0 | NO_EVT_OUTPUT | No event output when using the resynchronized or synchronous path |
| 0x1 | RISING_EDGE | Event detection occurs only on the rising edge of the signal from the event generator |
| 0x2 | FALLING_EDGE | Event detection occurs only on the falling edge of the signal from the event generator |
| 0x3 | BOTH_EDGES | Event detection occurs on both the rising and falling edges of the signal from the event generator |
Bits 9:8 – PATH[1:0] Path Selection
This bit field controls which path will be used for channel n.
Note: The path choice can be limited by
the event user. Refer to the Event Users section for further
information.
| Value | Name | Description |
|---|---|---|
| 0x0 | SYNCHRONOUS | Synchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| 0x2 | ASYNCHRONOUS | Asynchronous path |
| 0x3 | — | Reserved |
Bits 6:0 – EVGEN[6:0] Event Generator
| Value | Name | Description |
|---|---|---|
| 0x00 | OFF | Event channel n is disabled. |
| 0x01 | OSC32KCTRL_CLKFAIL | XOSC32K Failure |
| 0x02 | SUPC_MVIO | The voltage level on VDDIO2 is insufficient for communication |
| 0x03 | SUPC_VLM | Voltage Level Monitor is triggered |
| 0x04 | RTC_CMP_0 | Compare Match 0 overflow |
| 0x05 | RTC_CMP_1 | Compare Match 1 overflow |
| 0x06 | RTC_OVF | Counter overflow |
| 0x07 | RTC_PER_0 | Periodic event 0 |
| 0x08 | RTC_PER_1 | Periodic event 1 |
| 0x09 | RTC_PER_2 | Periodic event 2 |
| 0x0A | RTC_PER_3 | Periodic event 3 |
| 0x0B | RTC_PER_4 | Periodic event 3 |
| 0x0C | RTC_PER_5 | Periodic event 5 |
| 0x0D | RTC_PER_6 | Periodic event 6 |
| 0x0E | RTC_PER_7 | Periodic event 7 |
| 0x0F | EIC_EXTINT_0 | Periodic event 3 |
| 0x10 | EIC_EXTINT_1 | External Interrupt 1 Event Output |
| 0x11 | EIC_EXTINT_2 | External Interrupt 2 Event Output |
| 0x12 | EIC_EXTINT_3 | External Interrupt 3 Event Output |
| 0x13 | EIC_EXTINT_4 | External Interrupt 4 Event Output |
| 0x14 | EIC_EXTINT_5 | External Interrupt 5 Event Output |
| 0x15 | EIC_EXTINT_6 | External Interrupt 6 Event Output |
| 0x16 | EIC_EXTINT_7 | External Interrupt 7 Event Output |
| 0x17 | EIC_EXTINT_8 | External Interrupt 8 Event Output |
| 0x18 | EIC_EXTINT_9 | External Interrupt 9 Event Output |
| 0x19 | EIC_EXTINT_10 | External Interrupt 10 Event Output |
| 0x1A | EIC_EXTINT_11 | External Interrupt 11 Event Output |
| 0x1B | EIC_EXTINT_12 | External Interrupt 12 Event Output |
| 0x1C | EIC_EXTINT_13 | External Interrupt 13 Event Output |
| 0x1D | EIC_EXTINT_14 | External Interrupt 14 Event Output |
| 0x1E | EIC_EXTINT_15 | External Interrupt 15 Event Output |
| 0x1F | DMAC_CH_0 | Transfer on channel 0 is complete |
| 0x20 | DMAC_CH_1 | Transfer on channel 1 is complete |
| 0x21 | TC0_OVF | TC0 Overflow |
| 0x22 | TC0_MC_0 | TC0 Match/Compare 0 |
| 0x23 | TC0_MC_1 | TC0 Match/Compare 1 |
| 0x24 | TC1_OVF | TC1 Overflow |
| 0x25 | TC1_MC_0 | TC1 Match/Compare 0 |
| 0x26 | TC1_MC_1 | TC1 Match/Compare 1 |
| 0x27 | TC2_OVF | TC2 Overflow/Underflow |
| 0x28 | TC2_MC_0 | TC2 Match/Compare 0 |
| 0x29 | TC2_MC_1 | TC2 Match/Compare 1 |
| 0x2A | TCC0_OVF | TCC0 Overflow/Underflow |
| 0x2B | TCC0_TRG | TCC0 Trigger |
| 0x2C | TCC0_CNT | TCC0 Count |
| 0x2D | TCC0_MC_0 | TCC0 Match/Compare 0 |
| 0x2E | TCC0_MC_1 | TCC0 Match/Compare 1 |
| 0x2F | TCC0_MC_2 | TCC0 Match/Compare 2 |
| 0x30 | TCC0_MC_3 | TCC0 Match/Compare 3 |
| 0x31 | ADC0_RESRDY | ADC0 Result ready |
| 0x32 | ADC0_SAMPRDY | ADC0 Sample ready |
| 0x33 | ADC0_WCMP | ADC0 Window compare |
| 0x34 | AC0_COMP_0 | AC0 Compare 0 |
| 0x35 | AC0_COMP_1 | AC0 Compare 1 |
| 0x36 | AC0_WIN_0 | AC0 Window n inside/outside status |
| 0x37 | CCL_LUTOUT_0 | CCL LUT Out 0 |
| 0x38 | CCL_LUTOUT_1 | CCL LUT Out 1 |
| 0x39 | CCL_LUTOUT_2 | CCL LUT Out 2 |
| 0x3A | CCL_LUTOUT_3 | CCL LUT Out 3 |
| 0x3C | PAC_ACCERR | PAC Access Error |
| Other | — | Reserved |