25.4.3.1 Non-Maskable Interrupt (NMI)

The non-maskable interrupt pin can also generate an interrupt-on-edge or level detection, but it is configured with the dedicated NMI Control (NMICTRL) register. To select the sense for NMI, write to the NMISENSE bit group in the NMI Control (NMICTRL) register. NMI filtering is enabled by writing a ‘1’ to the NMI Filter Enable (NMIFILTEN) bit in the NMI Control (NMICTRL) register.

If edge detection or filtering is required, enable GCLK_EIC or CLK_OSC32K.

NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC module is not required to be enabled.

When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear (NMIFLAG) register is set. NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when set.