7 PCI-SIG TxPLL Electrical Compliance Test
(Ask a Question)Due to variations in board topologies, it might be necessary to adjust the Tx amplitude
characteristics to ensure compliance with electrical requirements of Peripheral
Component Interconnect Special Interest Group (PCI-SIG). The following fields, of the
SER_DRV_CTRL_M# register, are available to provide this control:
- TXDRVTRIM_FS_#P#B_M#
- TXDRVTRIM_HS_0DB_M#
- #P#B indicates the requested amount of de-emphasis
- M# indicates the requested TxSwing value
These register fields consist of two 3-bit controls:
- The most significant 3 bits control the cursor amplitude. Increasing this value by 1 (for example, from 4 to 5) increases the amplitude and height of the inner eye by 20 mV, approximately. Decreasing this value by 1 has the opposite effect.
- The least significant 3 bits control the post-cursor amplitude. Increasing this value by 1 (for example, from 4 to 5) increases the amplitude by approximately 20 mV and decreases the height of the inner eye by the same amount. Decreasing the value by 1 has the opposite effect.
To pass the PCISIG's Tx PLL bandwidth electrical compliance test on the ICICLE kit, the
following settings were used:
- TxMARGIN was set to 0x0 and TXSWING was set to 0x1.
- Modified the register field TXDRVTRIM_FS_3P5DB_M0 from 0x0A to 0x00. This lowered the total amplitude by 75 mV.
- Modified the register field TXDRVTRIM_FS_6P0DB_M0 from 0x24 to 0x13.