4 Configuration Registers

The PCIe settings should be reconfigured through 32-bit wide configuration space registers, listed as follows:

  • Information registers, which provide device, system, and bridge identification information
  • Bridge configuration registers, which enable configuration of the bridge functionality. These include:
    • Read-only registers that report control and status registers to the AXI4 bus
    • Bridge settings that must be configured at power-up, such as local interrupt mapping
  • Control/status registers, which are used by the AXI4 bus to control bridge behavior during an operation
  • Power management registers, which configure the power management capabilities of the bridge
  • Address mapping registers, which provide address mapping for AXI4 master and slave windows used for address translation
  • Root port and Endpoint interrupt registers
  • For Root port, user should use the APB register space to toggle or control the PERSTn output port
  • PCIe control and status registers, which enable the local processor to check the PCIe interface status. These read-only registers enable the local processor to detect the initialization of the bridge’s PCIe interface and monitor PCI link events.

Some registers are hardwired to a fixed value within the embedded PCIESS block

In Endpoint mode, PCIESS core issues interrupts to the Host processor (over the PCIe domain) for the following events:

  • DMA transfer end or error
  • Address Translation doorbell or error
  • Local interrupts (through local_interrupt_in[7:0] input port by local processor)

When one of the preceding events occurs, the source of the interrupt is reported in the ISTATUS_HOST register. The Host processor masks or enables each interrupt source independently by setting or clearing the corresponding bit in the IMASK_HOST register. If one or more ISTATUS_HOST interrupt sources are active and not masked by IMASK_HOST, the Bridge IP core issues an interrupt towards the Host Processor (over the PCIe domain). The interrupt is sent using Message Signaled Interrupt (MSI) if the PCIe host processor has enabled MSI, otherwise INT messages are used.

IMASK_HOST - Host Processor Interrupt Mask (For EndPoint only): Integration does not hardwire this register by Core Constants so it is read or write and its default value after reset is 32'h0. Setting a bit enables the associated interrupt source and clearing a bit masks the interrupt source.

ISTATUS_HOST: This is a read/write/clear register; the register’s bits are automatically set when the corresponding interrupt source is activated. Each source is independent, and thus multiple sources may be active simultaneously. The host processor monitors and clears status bits: writing 1 clears a bit, writing 0 has no effect.

The ISTATUS_HOST register is composed of the following bits for various interrupt sources:

  • DMA_END Bit [7:0]: reports that a DMA transfer is ended. Bit number “i” corresponds to DMA Engine number “i”
  • DMA_ERROR Bit [15:8]: reports that an error occurred during a DMA transfer. Bit number “i” corresponds to DMA Engine number “i”.
  • A_ATR_EVT Bit [19:16]: reports AXI Address Translation events (see ISTATUS_LOCAL for the same definition)
  • P_ATR_EVT Bit [23:20]: reports PCIe Address Translation events (see ISTATUS_LOCAL for the same definition)
  • INT_REQUEST Bit [31:24]: reports interrupt requests from the local processor (in this endpoint) to the Host Processor

When the PCIe is in Endpoint Mode, the local processor can drive up to eight interrupt sources high by generating a pulse (high) on the local_interrupt_in [7:0] input port and can drive those interrupt sources low by writing 1 to corresponding bits in this field.

For information about Configuration registers, see respective PolarFire Device Register Map or PolarFire SoC Register Map.