5 PCIe Configuration Space

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The following tables list the layout of the PCI express configuration space and provides the mapping for each register in the space.

Table 5-1. PCI Configuration Space
Offset	Description
0x00 to 0x03C	Type0 (endpoint) or Type1 (Root port/Bridge/Switch) Standard PCI configuration header
0x040 to 0x07C	Reserved
0x080 to 0x0B8	PCI Express Capability
0x0BC to 0x0CC	Reserved
0x0DC	Reserved
0x0E0 to 0x0F4	MSI Capability
0x0F8 to 0x0FC	PCI Power Management Capability

Table 5-2. PCI Express Capability Structure
Byte Offset	Bit Number
	31:24	23:16	15:8	7:0
0x080	Capability Register		Next capability Pointer	Capability ID
0x084	Device capabilities
0x088	Device status		Device control
0x08C	Link capabilities
0x090	Link status		Link control
0x094	Slot capabilities
0x098	Slot status		Slot control
0x09C	Root capabilities		Root control
0x0A0	Root Status
0x0A4	Device capabilities 2
0x0A8	Device status 2		Device control 2
0x0AC	Link capabilities 2
0x0B0	Link status 2		Link control 2
0x0B4	Slot capabilities 2
0x0B8	Slot status 2		Slot control 2

Table 5-3. MSI Capability Structure
Byte Offset	Bit Number
	31:24	23:16	15:8	7:0
0x0E0	Message Control		Next pointer	Capability ID
0x0E4	Message Address
0x0E8	Message Upper Address
0x0EC			Message Data

Table 5-4. Power management Capability Structure
Byte Offset	Bit Number
	31:24	23:16	15:8	7:0
0x0F8	Power management capabilities		Next item pointer	Capability ID
0x0FC	Data	PMCSR_BSE bridge support extensions	Power management control and status registers

Table 5-5. PCI Express Extended Configuration Space
Offset	Description
0x100 to 0x104	Vendor-specific capability with VSECID = 1556h; RevID = 1h
0x108 to 0x10C	Latency Tolerance Reporting capability
0x200 to 0x234	Advanced Error Reporting capability

Table 5-6. Vendor Specific Extended Capability Structure
Byte Offset	Bit Number
	31:24	23:16	15:8	7:0
0x100	Vendor-Specific Extended Capability Header
0x104	Vendor-Specific Header

Table 5-7. Latency Tolerance Reporting Capability Structure
Byte Offset	Bit Number
	31:24	23:16	15:8	7:0
0x108	PCI Express Extended Capability Header
0x10C	Max No-Snoop Latency Register		Max Snoop Latency Register

Table 5-8. Advanced Error Reporting Capability Structure
Byte Offset	Bit Number
	31:24	23:16	15:8	7:0
0x200	PCI Express Enhanced Capability Header
0x204	Uncorrectable Error Status Register
0x208	Uncorrectable Error Mask Register
0x20C	Uncorrectable Error Severity Register
0x210	Correctable Error Status Register
0x214	Correctable Error Mask Register
0x218	Advanced Error Capabilities and Control Register
0x21C	Header Log Register
0x22C	Root Error Command
0x230	Root Error Status
0x234	Error Source Identification Register

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