8 Revision History

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The revision history table describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 8-1. Revision History
Revision	Date	Description
J	05/2025	The following is a summary of changes made in the revision. Changed the width of PCIESS_AXI_#_M_ARSIZE, PCIESS_AXI_#_M_AWSIZE, PCIESS_AXI_#_S_ARSIZE, and PCIESS_AXI_#_S_AWSIZE ports to [2:0] in PCIESS Port List. Updated the note under Table 3-2, in the section PCIe Configurator, by adding the frequency range supported by the PCIe APB_S_CLK.
H	05/2024	The following is a summary of changes made in the revision. Replaced XpressRICH3-AXI with PCIESS in the Configuration Registers section
G	03/2024	The following is a summary of changes made in the revision. Added PCI-SIG TxPLL Electrical Compliance Test which describes the registers that can be used to pass the compliance test.
F	01/2024	The following is a summary of changes made in the revision. De-featured support on PCIe Subsystem memory ECC reporting. See ECC. Removed information about SECDED. For more information about defeaturing of PCIe SECDED reporting, see Change Impact Analysis. Updated the descriptions of PCIE_#_M_RDERR, PCIE_#_M_WDERR, PCIE_#_S_RDERR, and PCIE_#_S_WDERR ports. See PCIESS Port List.
E	09/2023	The following is a summary of changes made in the revision. Changed the document title to “PolarFire Family PCI Express” and added support for RT PolarFire throughout the document. Added information about PCIe to AXI4 outstanding transaction. See AXI Master Write Transactions, AXI Master Read Transactions, and AXI Slave Read Transactions. Added information about debug recommendations when LTSSM does not reach L0. See Low-Power States. Updated information about PCIe MSS. Added links to PolarFire FPGA PCIe Endpoint DDR3L DDR4 Memory Controller Data Plane and PolarFire FPGA PCIe Root Port Application Note in PCIe Subsystem Performance for throughput details in the end point and root port configurations. Added information about mapping of interrupt[7:0]. See Configuration Registers. Updated information about power management, interrupts, and auxiliary settings. See PCIe Configurator.
D	12/2022	The following is a summary of changes made in the revision. Updated the GitHub links in the document. Added a note in PCIe Simulation section. Updated information about interrupts. See PCIe Configurator.
C	04/2022	Added information about PERSTn signal when PCIe is configured as Root port. See Using PERSTn When PCIe is Configured as a Root Port.
B	01/2022	The following is a summary of changes made in the revision. Information about Figure 2 was updated. Information about low-power operation state L2/P2 was removed as it is defeatured. The revision history tables of both the user guides are retained here for the future reference. For information, see Table 2and Table 3.
A	08/2021	The first publication of the document. This user guide was created by merging the following documents: UG0685: PolarFire FPGA PCI Express User Guide UG0920: PolarFire SoC FPGA PCI Express User Guide

The following revision history table describes the changes that were implemented in the UG0685: PolarFire FPGA PCI Express User Guide document. The changes are listed by revision.

Note: UG0685: PolarFire FPGA PCI Express User Guide document is now obsolete and the information in the document has been migrated to PolarFire Family PCI Express User Guide.

Table 8-2. Revision History of UG0685: PolarFire FPGA PCI Express User Guide
Revision	Date	Description
Revision 10.0	4/21	The following is a summary of the changes in the revision. Information about PCIE_#_INTERUPT[7:0] port description was updated. See PCIESS Port List table. Information about Bus Functional Model was updated. Information about MSI Capability Structure was updated. See MSI Capability Structure table. Information about PERST_N signal was added. See PCIe Power-Up. Reference to information about how to debug PCIe was added. See Libero Configurators.
Revision 9.0	9/20	The following is a summary of the changes in the revision. Information about signal width of AWBURST, ARBURST, AWID, and AWLEN was updated. See PCIESS Port List table. Information about using of embedded DLL in fabric interface was updated. See PCIe General Settings table.
Revision 8.0	5/20	The following is a summary of the changes in the revision. Information about SEC_ERROR_EVENT_CNT and DED_ERROR_EVENT_CNT counter registers was updated. See ECC. Information about unused PCIe lanes were updated. See Legal Combinations of PCIe and XCVR Protocols figure. Information about DLUP_EXIT signal was updated. See PCIESS Port List table.
Revision 7.0	4/19	The following is a summary of the changes in the revision. Structural changes were made throughout the document. Information about PCIe general settings was updated. Information about PCIESS_AXI_#_M_BRESP[1:0] was updated. See PCIESS Port List table. Information about PCIE_#_M_RDERR and PCIE_#_M_WDERR was updated. See PCIESS Port List table. Information about PCIE_#_INTERUPT[7:0] port was updated. See PCIESS Port List table.
Revision 6.0	10/18	The following is a summary of the changes in the revision. Information about port description was updated. See PCIESS Port List table. Information about DMA source and destination address register descriptions was updated. See Scatter-Gather DMA Descriptors table. Information about user-supplied clock constraint was added. See Design Constraints. Information about Transmitter was updated. Information about how to enable ECC after PCIe enumeration was added. See ECC.
Revision 5.0	7/18	The document was updated for Libero SoC PolarFire v2.2 release.
Revision 4.0	4/18	The following is a summary of the changes in the revision. Information about AXI split transactions was added. See Conversion Between PCIe and AXI Transactions. Information about AXI limitation was added. See AXI4 Limitations. Information about AXI Master and Slave Throughput was added. See PCIe AXI Master IF Throughput and PCIe AXI Slave IF Throughput. Information about wake signals was updated. See PCIe Interrupts and Auxiliary Settings table. Information about PCIe translation address was updated. See PCIe Master Settings and PCIe Slave Settings tables.
Revision 3.0	11/17	The following is a summary of the changes in the revision. Information about PCIe Subsystem memory buffers was added. See ECC. Information about PCIE_#_TL_CLK_125MHz port name was updated. See PCIESS Port List table. Information about register content of the PCIe configuration space was added. See PCIe Configuration Space. Updated Configuration Registers chapter. A note about PCIe BFM simulation model was added in PCIe Simulation section.
Revision 2.0	6/17	The following is a summary of the changes in the revision. Information about how to use VIP models was added. See PCIe Simulation. Information about DMA Descriptors was added. See DMA Transfers. Updated PCIe Configurator screen shots.
Revision 1.0	2/17	The first publication of UG0685: PolarFire FPGA PCI Express User Guide

The following revision history table describes the changes that were implemented in the UG0920: PolarFire SoC FPGA PCI Express User Guide document. The changes are listed by revision.

Note: UG0920: PolarFire SoC FPGA PCI Express User Guide document is now obsolete and the information in the document has been migrated to PolarFire Family PCI Express User Guide.

Table 8-3. Revision History of UG0920: PolarFire SoC FPGA PCI Express User Guide
Revision	Date	Description
Revision 3.0	5/21	The following is a summary of the changes in the revision. Information about PCIE_#_INTERUPT[7:0] port description was updated. See PCIESS Port List table. Information about Bus Functional Model was updated. Information about MSI Capability Structure was updated. See MSI Capability Structure table. Information about PERST_N signal was added. See PCIe Power-Up. Reference to information about how to debug PCIe was added. See Libero Configurators.
Revision 2.0	9/20	The following is a summary of the changes in the revision. Information about signal width of AWBURST, ARBURST, AWID, and AWLEN was updated. See PCIESS Port List table. Information about using of embedded DLL in fabric interface was updated. See PCIe General Settings table.
Revision 1.0	5/20	The first publication of UG0920: PolarFire SoC FPGA PCI Express User Guide