Introduction
(Ask a Question)PCI Express (PCIe®) is a scalable, high-bandwidth serial interconnect technology that maintains compatibility with existing PCI systems. Microchip’s PolarFire® Family of FPGAs contain fully integrated PCIe endpoint and root port subsystems with optimized embedded controller blocks that use the physical layer interface of the transceiver for the PCI Express (PIPE) interconnection within the transceiver block.
This user guide describes the PCIe subsystem available in the PolarFire family of devices. The FPGA fabric is common to the PolarFire family, which consists of the following FPGA devices.
- PolarFire FPGAs
- Microchip's PolarFire® FPGAs are the fifth-generation family of non-volatile FPGA devices, built on state-of-the-art 28 nm non-volatile process technology. PolarFire FPGAs deliver the lowest power at mid-range densities. PolarFire FPGAs lower the cost of mid-range FPGAs by integrating the industry’s lowest power FPGA fabric, lowest power 12.7 Gbps transceiver lane, built-in low power dual PCI Express Gen2 (EP/RP), and, on select data security (S) devices, an integrated low-power crypto co-processor.
- PolarFire SoC FPGAs
- Microchip's PolarFire SoC FPGAs are the fifth-generation family of non-volatile SoC FPGA devices, built on state-of-the-art 28 nm non-volatile process technology. The PolarFire SoC family offers industry's first RISC-V based SoC FPGAs capable of running Linux®. It combines a powerful 64-bit 5x core RISC-V Microprocessor Subsystem (MSS), based on SiFive’s U54-MC family, with the PolarFire FPGA fabric in a single device.
- RT PolarFire FPGAs
- Microchip's RT PolarFire® FPGAs combine our 60 years of space flight heritage with the industry’s lowest-power PolarFire FPGA family to enable new capabilities for space and mission-critical applications. RT PolarFire FPGA family includes RTPF500T, RTPF500TL, RTPF500TS, RTPF500TLS, RTPF500ZT, RTPF500ZTL, RTPF500ZTS, and RTPF500ZTLS devices.
Each device in the PolarFire family includes two embedded PCIe subsystem (PCIESS) blocks that can be configured using the PF_PCIE configurator in the Libero® SoC software.
The following table summarizes the PCIESS components available in the PolarFire family.
| Fabric Component | PolarFire FPGA (MPF) | RT PolarFire FPGA (RTPF) | PolarFire SoC FPGA (MPFS) | |
|---|---|---|---|---|
| Physical layer of XCVR | ✓ | ✓ | ✓ | |
| PCIe IP (Data link layer (DL) and Transaction layer (TL)) | ✓ | ✓ | ✓ | |
| Bridge Layer | ✓ | ✓ | ✓ | |
| AXI4 Layer | ✓ | ✓ | ✓ | |
| MSS Component | ||||
| PCIe MSS | — | — | ✓ | |
The PCIESS supports AMBA AXI4 master/slave user interface functionality between the AXI4 and PCIe systems.
The PCIESS is compliant with the following standards: