1.3 Data Gating

The outputs of the four multiplexers from the input stage are directed to the desired logic function through the gating stage of the CLC. Each data gate can direct any combination of multiplexer outputs. The data gating stage both directs the inputs and can invert them. Figure 1-2 displays the data-gating stage.

The CLCGLSx registers determine the polarity of each of the inputs to the data gating stage; the LCGxPOL bit determines the polarity of the output of each data gating stage.