34.9 Parallel Programming Characteristics

Table 34-12. Parallel Programming Characteristics, VCC = 5V ± 10%
SymbolParameterMin.MaxUnits
VPPProgramming Enable Voltage11.512.5V
IPPProgramming Enable Current-250μA
tDVXHData and Control Valid before XTAL1 High67-ns
tXLXHXTAL1 Low to XTAL1 High200-ns
tXHXLXTAL1 Pulse Width High150-ns
tXLDXData and Control Hold after XTAL1 Low67-ns
tXLWLXTAL1 Low to WR Low0-ns
tXLPHXTAL1 Low to PAGEL high0-ns
tPLXHPAGEL low to XTAL1 high150-ns
tBVPHBS1 Valid before PAGEL High67-ns
tPHPLPAGEL Pulse Width High150-ns
tPLBXBS1 Hold after PAGEL Low67-ns
tWLBXBS2/1 Hold after RDY/BSY high67-ns
tPLWLPAGEL Low to WR Low67-ns
tBVWLBS1 Valid to WR Low67-ns
tWLWHWR Pulse Width Low150-ns
tWLRLWR Low to RDY/BSY Low01μs
tWLRHWR Low to RDY/BSY High(1)3.23.4ms
tWLRH_CEWR Low to RDY/BSY High for Chip Erase(2)9.810.5ms
tXLOLXTAL1 Low to OE Low0-ns
tBVDVBS1 Valid to DATA valid0350ns
tOLDVOE Low to DATA Valid-350ns
tOHDZOE High to DATA Tri-stated-250ns
Note:
  1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
  2. tWLRH_CE is valid for the Chip Erase command.
Figure 34-6. Parallel Programming Timing, Including some General Timing Requirements
Figure 34-7. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note: The timing requirements shown in Parallel Programming Characteristics (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation
Figure 34-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements
Note: The timing requirements shown in Parallel Programming Characteristics (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.