34.6 SPI Timing Characteristics

Table 34-9. SPI Timing Parameters
DescriptionModeMin.TypMaxUnits
SCK periodMaster-See Table. Relationship Between SCK and the Oscillator Frequency in "SPCR – SPI Control Register"-ns
SCK high/lowMaster-50% duty cycle-
Rise/Fall timeMaster-3.6-
SetupMaster-10-
HoldMaster-10-
Out to SCKMaster-0.5 • tsck-
SCK to outMaster-10-
SCK to out highMaster-10-
SS low to outSlave-15-
SCK periodSlave4 • tck--
SCK high/low(1)Slave2 • tck--
Rise/Fall timeSlave--1600
SetupSlave10--
HoldSlavetck--
SCK to outSlave-15-
SCK to SS highSlave20--
SS high to tri-stateSlave10-
SS low to SCKSlave2 • tck--
Note: In SPI Programming mode the minimum SCK high/low period is:

  • 2 • tCLCLCL for fCK < 12MHz

  • 3 • tCLCL for fCK > 12MHz
Figure 34-3. SPI Interface Timing Requirements (Master Mode)
Figure 34-4. SPI Interface Timing Requirements (Slave Mode)