34.7 Two-wire Serial Interface Characteristics
Table in this section describes the requirements for devices connected to the 2-wire Serial Bus. The 2-wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 34-5.
Symbol | Parameter | Condition | Min. | Max | Units |
---|---|---|---|---|---|
VIL | Input Low-voltage | -0.5 | 0.3 VCC | V | |
VIH | Input High-voltage | 0.7 VCC | VCC + 0.5 | V | |
Vhys(1) | Hysteresis of Schmitt Trigger Inputs | 0.05 VCC(2) | – | V | |
VOL(1) | Output Low-voltage | 3mA sink current | 0 | 0.4 | V |
tr(1) | Rise Time for both SDA and SCL | 20 + 0.1Cb(3)(2) | 300 | ns | |
tof(1) | Output Fall Time from VIHmin to VILmax | 10pF < Cb < 400pF(3) | 20 + 0.1Cb(3)(2) | 250 | ns |
tSP(1) | Spikes Suppressed by Input Filter | 0 | 50(2) | ns | |
Ii | Input Current each I/O Pin | 0.1VCC < Vi < 0.9VCC | -10 | 10 | μA |
Ci(1) | Capacitance for each I/O Pin | – | 10 | pF | |
fSCL | SCL Clock Frequency | fCK(4) > max(16fSCL, 250kHz)(5) | 0 | 400 | kHz |
Rp | Value of Pull-up resistor | fSCL ≤ 100kHz | |||
fSCL > 100kHz | |||||
tHD;STA | Hold Time (repeated) START Condition | fSCL ≤ 100kHz | 4.0 | – | μs |
fSCL > 100kHz | 0.6 | – | μs | ||
tLOW | Low Period of the SCL Clock | fSCL ≤ 100kHz | 4.7 | – | μs |
fSCL > 100kHz | 1.3 | – | μs | ||
tHIGH | High period of the SCL clock | fSCL ≤ 100kHz | 4.0 | – | μs |
fSCL > 100kHz | 0.6 | – | μs | ||
tSU;STA | Set-up time for a repeated START condition | fSCL ≤ 100kHz | 4.7 | – | μs |
fSCL > 100kHz | 0.6 | – | μs | ||
tHD;DAT | Data hold time | fSCL ≤ 100kHz | 0 | 3.45 | μs |
fSCL > 100kHz | 0 | 0.9 | μs | ||
tSU;DAT | Data setup time | fSCL ≤ 100kHz | 250 | – | ns |
fSCL > 100kHz | 100 | – | ns | ||
tSU;STO | Setup time for STOP condition | fSCL ≤ 100kHz | 4.0 | – | μs |
fSCL > 100kHz | 0.6 | – | μs | ||
tBUF | Bus free time between a STOP and START condition | fSCL ≤ 100kHz | 4.7 | – | μs |
fSCL > 100kHz | 1.3 | – | μs |
Note:
- This parameter is characterized and not 100% tested.
- Required only for fSCL > 100kHz.
- Cb = capacitance of one bus line in pF.
- fCK = CPU clock frequency.
- This requirement applies to all 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement.