34.7 Two-wire Serial Interface Characteristics

Table in this section describes the requirements for devices connected to the 2-wire Serial Bus. The 2-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 34-5.

Table 34-10. Two-wire Serial Bus Requirements
SymbolParameterConditionMin.MaxUnits
VILInput Low-voltage-0.50.3 VCCV
VIHInput High-voltage0.7 VCCVCC + 0.5V
Vhys(1)Hysteresis of Schmitt Trigger Inputs0.05 VCC(2)V
VOL(1)Output Low-voltage3mA sink current00.4V
tr(1)Rise Time for both SDA and SCL20 + 0.1Cb(3)(2)300ns
tof(1)Output Fall Time from VIHmin to VILmax10pF < Cb < 400pF(3)20 + 0.1Cb(3)(2)250ns
tSP(1)Spikes Suppressed by Input Filter050(2)ns
IiInput Current each I/O Pin0.1VCC < Vi < 0.9VCC-1010μA
Ci(1)Capacitance for each I/O Pin10pF
fSCLSCL Clock FrequencyfCK(4) > max(16fSCL, 250kHz)(5)0400kHz
RpValue of Pull-up resistorfSCL ≤ 100kHz
VCC0.4V3mA
1000nsCb
Ω
fSCL > 100kHz
VCC0.4V3mA
300nsCb
Ω
tHD;STAHold Time (repeated) START ConditionfSCL ≤ 100kHz4.0μs
fSCL > 100kHz0.6μs
tLOWLow Period of the SCL ClockfSCL ≤ 100kHz4.7μs
fSCL > 100kHz1.3μs
tHIGHHigh period of the SCL clockfSCL ≤ 100kHz4.0μs
fSCL > 100kHz0.6μs
tSU;STASet-up time for a repeated START conditionfSCL ≤ 100kHz4.7μs
fSCL > 100kHz0.6μs
tHD;DATData hold timefSCL ≤ 100kHz03.45μs
fSCL > 100kHz00.9μs
tSU;DATData setup timefSCL ≤ 100kHz250ns
fSCL > 100kHz100ns
tSU;STOSetup time for STOP conditionfSCL ≤ 100kHz4.0μs
fSCL > 100kHz0.6μs
tBUFBus free time between a STOP and START conditionfSCL ≤ 100kHz4.7μs
fSCL > 100kHz1.3μs
Note:
  1. This parameter is characterized and not 100% tested.
  2. Required only for fSCL > 100kHz.
  3. Cb = capacitance of one bus line in pF.
  4. fCK = CPU clock frequency.
  5. This requirement applies to all 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement.
Figure 34-5. Two-wire Serial Bus Timing