16.4.1 Overview

The RSTC comprises an NRST pin manager and a Reset State manager. The RSTC clock is MD_SLCK (monitoring slow clock) generated by the always-on slow RC oscillator. The RSTC generates the following reset signals:

• Processor and peripherals reset line (also resets the Watchdog Timers)
• Coprocessor (second processor) reset line
• Embedded peripherals driven by the coprocessor
• Power Management Controller (PMC) reset line
• NRST pin

These reset signals are controlled by the RSTC, either on events generated by peripherals, events on NRST pin, watchdog fault or overflow, or on software action. The Reset State manager controls the generation of reset signals and provides a signal to the NRST manager when an assertion of the NRST pin is required.

The NRST manager asserts the NRST pin during a programmable time, thus controlling external device resets.

The Mode register (RSTC_MR), used to configure the RSTC, is powered by VDDBU.

The RSTC can reset separately the processor and its peripherals, and the coprocessor and its peripherals.