16.4.5 Managing Resets at Application Level

The device embeds only one Power Management Controller (PMC) shared by the two processor subsystems, i.e.:

• Subsystem 0 (Application Core)
• Subsystem 1 (Coprocessor Core)

After a power-up, the Subsystem 0 application configures the Subsystem 1 system clock (PMC). Then, the application code can be downloaded into the Subsystem 1 boot memory (SRAM1) and Subsystem 0 can then de-assert the Subsystem 1 reset lines through the RSTC.

Once the two subsystems are running, each one executes its firmware independently. If a reset source is enabled, it acts on the subsystems as described below. See the corresponding peripheral sections for further details on resets.

• VDDCORE Supply Monitor reset – Subsystem 0 and Subsystem 1 are reset.
• 32.768 kHz Crystal Oscillator Failure Detection reset – Only Subsystem 0 is reset.
• CPU Clock Failure Detection reset – Subsystem 0 and Subsystem 1 are reset.
• Watchdog 0 reset – Only Subsystem 0 is reset. The reset of the PMC can be configured with RSTC_MR.WDTPMC0.
• Watchdog 1 reset – Only Subsystem 0 is reset. The reset of the PMC can be configured with RSTC_MR.WDTPMC1.
• Software reset – Only Subsystem 0 is reset. The reset of the PMC can be configured with RSTC_MR.SFTPMCRS.
• VDD3V3 Supply Monitor reset – Subsystem 0 and Subsystem 1 are reset.
• User reset (NRST pin) – Subsystem 0 and Subsystem 1 are reset. To avoid this, the User reset must be configured to generate an interrupt and not a reset (RSTC_MR.URSTEN = 0 and RSTC_MR.URSTIEN = 1)