25.4.4 Erase Flash/SRAM Register
This is a write-once register and is only unlocked by a reset.
| Name: | SFR_ERASE_FLASH_SRAM |
| Offset: | 0xB0 |
| Reset: | 0x00000001 |
| Property: | Read/Write-Once |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRAM0 | HW_ERASE | ||||||||
| Access | R/WO | R/WO | |||||||
| Reset | 0 | 1 |
Bit 1 – SRAM0 Erase SRAM0 Content
| Value | Name | Description |
|---|---|---|
| 0 | NOT_DELETED | If HW_ERASE = 1, and HW erase signal assertion occurs, SRAM0 content is not deleted. |
| 1 | DELETED | If HW_ERASE = 1, and HW erase signal assertion occurs, SRAM0 content is deleted. |
Bit 0 – HW_ERASE PB2/Peripherals or Hardware Erase Signal Assignment
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Hardware erase signal disabled. PB2 pin can be used in GPIO or Peripheral IO mode. |
| 1 | ENABLE | Hardware erase signal enabled. PB2 pin is assigned to Flash erase function. |