25.4.3 Core Debug Configuration Register
| Name: | SFR_CORE_DEBUG_CFG |
| Offset: | 0xA0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| XTRG0 | XTRG1 | SWV | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – XTRG0 From Core 0 to Core 1 Cross Triggering
| Value | Description |
|---|---|
| 0 | Core 0 is not able to trigger an event on core 1. |
| 1 | Core 0 is able to trigger an event on core 1. |
Bit 1 – XTRG1 From Core 1 to Core 0 Cross Triggering
| Value | Description |
|---|---|
| 0 | Core 1 is not able to trigger an event on core 0. |
| 1 | Core 1 is able to trigger an event on core 0. |
Bit 0 – SWV SWV Selection
| Value | Description |
|---|---|
| 0 | swv_core0 is selected |
| 1 | swv_core1 is selected |