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Second-Generation Smart Energy Platform Solution including Integrated Metrology, Dual Arm® Cortex®-M4F Cores, Security and LCD Controller
Second-Generation Smart Energy Platform Solution including Integrated Metrology, Dual Arm® Cortex®-M4F Cores, Security and LCD Controller
Product Pages
PIC32CX1025MTSH PIC32CX2051MTSH PIC32CX5112MTSH
  1. Home
  2. 8 Memories
  3. 8.1 Embedded Memories
  4. 8.1.5 Embedded Flash
  5. 8.1.5.2 Memory Plane and Sector Organization
  6. 8.1.5.2.2 Flash Speed
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  • Description
  • Features
  • 1 Block Diagram
  • 2 Configuration Summary
  • 3 Package and Pinout
  • 4 Power Supply and Power Control
  • 5 Input/Output Lines
  • 6 Core and Interconnect
  • 7 Product Mapping and Peripheral Access
  • 8 Memories
    • 8.1 Embedded Memories
      • 8.1.1 Internal SRAM
      • 8.1.2 Cache Controller and Tightly Coupled Memory (TCM) Interface
      • 8.1.3 System ROM
      • 8.1.4 CPKCC ROM
      • 8.1.5 Embedded Flash
        • 8.1.5.1 Flash Overview
        • 8.1.5.2 Memory Plane and Sector Organization
          • 8.1.5.2.1 Secure Embedded Flash Controller (SEFC)
          • 8.1.5.2.2 Flash Speed
          • 8.1.5.2.3 Lock Regions
          • 8.1.5.2.4 Unique Identifier
          • 8.1.5.2.5 User Signature
          • 8.1.5.2.6 Application Core and Metrology Core Boot Process
    • 8.2 External Memories
  • 9 Safety and Security Features
  • 10 Real-Time Event Management
  • 11 Peripherals
  • 12 Cortex-M4 Processor (Arm)
  • 13 Flash Programming, Debug and Test Features
  • 14 ROM Code and Boot Strategies
  • 15 Supply Controller (SUPC)
  • 16 Reset Controller (RSTC)
  • 17 System Controller Write Protection (SYSCWP)
  • 18 Dual Watchdog Timer (DWDT)
  • 19 Clock Generator
  • 20 Power Management Controller (PMC)
  • 21 Parallel Input/Output Controller (PIO)
  • 22 Real-Time Clock (RTC)
  • 23 Real-time Timer (RTT)
  • 24 General Purpose Backup Registers (GPBR)
  • 25 Special Function Registers (SFR)
  • 26 Special Function Registers Backup (SFRBU)
  • 27 Bus Matrix (MATRIX)
  • 28 Chip Identifier (CHIPID)
  • 29 Secure Embedded Flash Controller (SEFC)
  • 30 Interprocessor Communication (IPC)
  • 31 Memory to Memory (MEM2MEM)
  • 32 Peripheral DMA Controller (PDC)
  • 33 Cortex-M Cache Controller (CMCC)
  • 34 Flexible Serial Communication Controller (FLEXCOM)
  • 35 Quad Serial Peripheral Interface (QSPI)
  • 36 Segment LCD Controller (SLCDC)
  • 37 Timer Counter (TC)
  • 38 Analog-to-Digital Converter (ADC) Controller
  • 39 Analog Comparator Controller (ACC)
  • 40 Advanced Encryption Standard (AES)
  • 41 Advanced Encryption Standard Bridge (AESB)
  • 42 Secure Hash Algorithm (SHA)
  • 43 True Random Number Generator (TRNG)
  • 44 Integrity Check Monitor (ICM)
  • 45 Classical Public Key Cryptography Controller (CPKCC)
  • 46 Energy Metering Analog Front End (EMAFE)
  • 47 Multi Channel Serial Peripheral Interface (MCSPI)
  • 48 Pulse Width Modulation Controller (PWM)
  • 49 Universal Asynchronous Receiver Transmitter (UART)
  • 50 Electrical Characteristics
  • 51 Mechanical Characteristics
  • 52 Marking
  • 53 Ordering Information
  • 54 Revision History
  • 55 Product Identification System
  • Microchip Information

8.1.5.2.2 Flash Speed

The user must set the number of Wait states depending on the frequency used.

For more details, refer to Embedded Flash Characteristics of the section Electrical Characteristics.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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