29.4.1 Embedded Flash Organization

The SEFC interfaces between an embedded Flash memory plane and the internal bus.

A memory subsystem is composed of:

• The 256-KByte, 512-KByte or 1-MByte main area memory plane organized in several pages of 512 bytes for the code and data
• A separate 4-Kbyte memory area which includes the unique chip identifier
• A separate 32-Kbyte (8 x 4K) memory area for the user signature, cryptographic keys and One Time Programmable block
• Two 128-bit read buffers for code read optimization
• Two 128-bit read buffers for code loop optimization
• One 128-bit read buffer for data read optimization
• One write-only buffer equal to the page size that manages page programming along the full flash memory address space
• Lock bits used to protect write/erase operation on several pages (lock region); a lock bit is associated with a lock region composed of several pages in the memory plane
• General-purpose non-volatile memory bits (GPNVM) that may be set and cleared through the SEFC interface (only Plane 0 GPNVM bits are active)

A device may feature more than one memory subsystem. Refer to the table “Configuration Summary” for the device memory configuration.

The embedded Flash size, the page size, the organization of lock regions and the definition of GPNVM bits are specific to the device. The SEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’ command was issued by the application (see Get Flash Descriptor Command).