29.4.2 Read Operations

The SEFC manages embedded Flash reads. Performance is increased when the processor is running in Thumb-2 mode by means of the 128-bit-wide memory interface.

The Flash memory is accessible through 8-, 16- and 32-bit reads.

The read operations can be performed with or without wait states. Wait states must be programmed in the EEFC_FMR.FWS field. Defining FWS as 0 enables the single-cycle access of the embedded Flash. For more details, refer to the section “Electrical Characteristics” of this datasheet.

Reading in the memory plane stalls the bus when it is being programmed or erased except when the suspend feature is used.

Reading in one Flash memory plane through one SEFC does not stall the bus when a second Flash memory plane is being programmed or erased through the second SEFC.