50.9.4.1 CoreMark™

  • Core 0 running CoreMark from different memory modes:
    • Flash with cache disabled
    • Flash with cache enabled
  • Core 1 running CoreMark out of SRAM1 (Instruction) and SRAM2 (Data)

PLLA and PLLB are used to generate the required frequencies.

Table 50-62. Current Consumption
Cores Clock/Main Clock (MHz)

Core 0 Cache Disabled

Core 1 SRAM

Core 0 Cache Enabled

Core 1 SRAM

Unit
Core 0 Clock/Main Clock 
MCK0, MCK0DIV, MCK0DIV2Core 1 Clock / Main Clock MCK1, MCK1DIVAMP1AMP2AMP1AMP2
200/200, 100, 200240/240, 12070507562mA
100/100, 100, 100120/120, 12047304936
50/50, 50, 5060/60, 60, 6035203421