18.4.1 Configuration

The DWDT is supplied with VDDCORE.

Each watchdog monitoring period (period corresponding to an overflow of the watchdog counter) is independent and can be configured by writing the field PERIOD in the Window Level register (WDT1_WL or WDT0_WL).

The WDT0 clock period is defined by MD_SLCK divided by 2(7-WDT0_IL.PRESC).

The WDT1 clock period is defined by MD_SLCK divided by 2(7-WDT1_IL.PRESC).

For each watchdog, the following parameters can be defined:

  • PRESC (Prescaler value)–Defines the clock of the 12-bit down counter. The watchdog counter is decreased by 1 each time the prescaler reaches the value defined by 2(7-WDTx_IL.PRESC).
  • PERIOD (Watchdog Monitoring Period)–Value loaded each time a watchdog reset command is asserted. Once the down counter reaches 0, a watchdog event is generated. This event leads to either a reset (if WDT0_MR.PERIODRST=1 or WDT1_MR.PERIODRST=1) or an interrupt (if WDT0_IMR.PERINT=1 or WDT1_IMR.PERINT=1).
  • RPTH (Repeat Threshold)–A watchdog restart done before the repeat threshold is elapsed leads to a repeat violation. A repeat violation leads to either a reset (if WDT0_MR.RPTHRST=1 or WDT1_MR.RPTHRST=1) or an interrupt (if WDT0_IMR.RPTHINT=1 or WDT1_IMR.RPTHINT=1).
  • LVLTH (Interrupt Threshold)–Threshold after which an interrupt is generated (if WDT0_IMR.LVLINT=1 or WDT1_IMR.LVLINT=1).

After a processor reset, the value of PERIOD is 0xFFF and the value of PRESC is 0x000, corresponding to the maximum value of the counter with the external reset generation enabled (PERIODRST at 1 after a backup reset). This means that watchdogs are running at reset, that is, at power-up. The user can either disable the WDT by setting WDT0_MR.WDDIS=1 and/or WDT1_MR.WDDIS=1 or reprogram the WDTs to meet the maximum watchdog period the application requires.

The WDT1 and the WDT0 embed securities to avoid programming out of range values. The following inequality must be verified, otherwise the configuration is canceled:

RPTH ≤ LVLTH < PERIOD

In addition, the WDT0 has the possibility to control the range of operation of the WDT1. It can limit the period, the repeat threshold and the interrupt level of the WDT1 by programming WDT1_LVLLIM, WDT1_RLIM and WDT1_PLIM.