49.6.2 UART Mode Register
| Name: | UART_MR |
| Offset: | 0x04 |
| Reset: | 0x00130000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OPT_CMPTH[2:0] | OPT_DUTY[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OPT_CLKDIV[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 1 | 1 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHMODE[1:0] | BRSRCCK | PAR[2:0] | OPTI_WKUP | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EDGESEL[1:0] | ACON | FILTER | OPT_DMOD | OPT_MDINV | OPT_RXINV | OPT_EN | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 30:28 – OPT_CMPTH[2:0] Receive Path Comparator Threshold
| Value | Name | Description |
|---|---|---|
| 0 | VDD3V3_DIV2 |
Comparator threshold is VDD3V3/2 volts. |
| 1 | VDD3V3_DIV2P5 |
Comparator threshold is VDD3V3/2.5 volts. |
| 2 | VDD3V3_DIV3P3 |
Comparator threshold is VDD3V3/3.3 volts. |
| 3 | VDD3V3_DIV5 |
Comparator threshold is VDD3V3/5 volts. |
| 4 | VDD3V3_DIV10 |
Comparator threshold is VDD3V3/10 volts. |
Bits 26:24 – OPT_DUTY[2:0] Optical Link Modulation Clock Duty Cycle
| Value | Name | Description |
|---|---|---|
| 0 | DUTY_50 |
Modulation clock duty cycle Is 50%. |
| 1 | DUTY_43P75 |
Modulation clock duty cycle Is 43.75%. |
| 2 | DUTY_37P5 |
Modulation clock duty cycle Is 37.5%. |
| 3 | DUTY_31P25 |
Modulation clock duty cycle Is 31.75%. |
| 4 | DUTY_25 |
Modulation clock duty cycle Is 25%. |
| 5 | DUTY_18P75 |
Modulation clock duty cycle Is 18.75%. |
| 6 | DUTY_12P5 |
Modulation clock duty cycle Is 12.5%. |
| 7 | DUTY_6P25 |
Modulation clock duty cycle Is 6.25%. |
Bits 20:16 – OPT_CLKDIV[4:0] Optical Link Clock Divider
| Value | Description |
|---|---|
| 0–31 |
The optical modulation clock frequency is defined by PLLACK / (8 * (OPT_CLKDIV + 8)). |
Bits 15:14 – CHMODE[1:0] Channel Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Normal mode |
| 1 | AUTOMATIC | Automatic echo |
| 2 | LOCAL_LOOPBACK | Local loopback |
| 3 | REMOTE_LOOPBACK | Remote loopback |
Bit 12 – BRSRCCK Baud Rate Source Clock
0 (PERIPH_CLK): The baud rate is driven by the peripheral clock
1 (GCLK): The baud rate is driven by a PMC-programmable clock GCLK (refer to section "Power Management Controller (PMC)").
Bits 11:9 – PAR[2:0] Parity Type
| Value | Name | Description |
|---|---|---|
| 0 | EVEN | Even parity |
| 1 | ODD | Odd parity |
| 2 | SPACE | Space: parity forced to 0 |
| 3 | MARK | Mark: parity forced to 1 |
| 4 | NO | No parity |
Bit 8 – OPTI_WKUP Optical Link Activity Wake-up Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | To detect any activity on the output of analog comparator, the clock is always active and OPT_EN must be written to 1. |
| 1 | ENABLED | If OPT_EN=0 and a logical 1 is detected after inversion (if RXINV=1) on analog comparator output, the clock if automatically enabled for all UART sub-modules. After a period of inactivity on URXD (time-out) the software can instruct the UART to disabled the clock of all sub-modules to reduce power consumption by applying the UART_CR.OPT_SLEEP command. |
Bits 7:6 – EDGESEL[1:0] Analog Comparator Output Edge Selection
| Value | Name | Description |
|---|---|---|
| 0 | RISING | UART_SR.ACE is set if a rising edge is detected on analog comparator output. |
| 1 | FALLING | UART_SR.ACE is set if a falling edge is detected on analog comparator output. |
| 2 | ANY_EDGE | UART_SR.ACE is set as soon as an edge is detected on analog comparator output. |
Bit 5 – ACON Analog Comparator Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | The analog comparator is disabled. If OPT_EN=1, the analog comparator is enabled. |
| 1 | ENABLED | The analog comparator is enabled. |
Bit 4 – FILTER Receiver Digital Filter
0 (DISABLED): UART does not filter the receive line.
1 (ENABLED): UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
Bit 3 – OPT_DMOD Optical Demodulation Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | The optical demodulator is disabled. External demodulation must be enabled. |
| 1 | ENABLED | The optical demodulator is enabled. |
Bit 2 – OPT_MDINV UART Modulated Data Inverted
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED |
The output of the modulator is not inverted. |
| 1 | ENABLED |
The output of the modulator is inverted. |
Bit 1 – OPT_RXINV UART Receive Data Inverted
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED |
The comparator data output is not inverted before entering UART. |
| 1 | ENABLED |
The comparator data output is inverted before entering UART. |
Bit 0 – OPT_EN UART Optical Interface Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | Disables the UART optical link. |
| 1 | ENABLED | Enables the UART optical link. |