The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Name:
UART_IMR
Offset:
0x10
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
ACE
Access
W
Reset
–
Bit
15
14
13
12
11
10
9
8
CMP
RXBUFF
TXBUFE
TXEMPTY
TIMEOUT
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
TXRDY
RXRDY
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
Bit 16 – ACE Mask Analog Comparator Event Interrupt
Bit 15 – CMP Mask Comparison Interrupt
Bit 12 – RXBUFF Mask RXBUFF Interrupt
Bit 11 – TXBUFE Mask TXBUFE Interrupt
Bit 9 – TXEMPTY Mask TXEMPTY Interrupt
Bit 8 – TIMEOUT Mask Time-out Interrupt
Bit 7 – PARE Mask Parity Error Interrupt
Bit 6 – FRAME Mask Framing Error Interrupt
Bit 5 – OVRE Mask Overrun Error Interrupt
Bit 4 – ENDTX Mask End of Transmit Interrupt
Bit 3 – ENDRX Mask End of Receive Transfer Interrupt
Bit 1 – TXRDY Mask TXRDY
Interrupt
Bit 0 – RXRDY Mask RXRDY Interrupt
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
