The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name:
UART_IDR
Offset:
0x0C
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
ACE
Access
W
Reset
–
Bit
15
14
13
12
11
10
9
8
CMP
RXBUFF
TXBUFE
TXEMPTY
TIMEOUT
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
TXRDY
RXRDY
Access
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
Bit 16 – ACE Disable Analog Comparator Event Interrupt
Bit 15 – CMP Disable Comparison Interrupt
Bit 12 – RXBUFF Disable Buffer Full Interrupt
Bit 11 – TXBUFE Disable Buffer Empty Interrupt
Bit 9 – TXEMPTY Disable TXEMPTY Interrupt
Bit 8 – TIMEOUT Disable Time-out Interrupt
Bit 7 – PARE Disable Parity Error Interrupt
Bit 6 – FRAME Disable Framing Error Interrupt
Bit 5 – OVRE Disable Overrun Error Interrupt
Bit 4 – ENDTX Disable End of Transmit Interrupt
Bit 3 – ENDRX Disable End of Receive Transfer Interrupt
Bit 1 – TXRDY Disable TXRDY Interrupt
Bit 0 – RXRDY Disable RXRDY Interrupt
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
