36.6.2.7 Frame Rate

The Frame Rate register (SLCDC_FRR) enables the generation of the frequency used by the SLCDC. It is done by a prescaler (division by 8, 16, 32, 64, 128, 256, 512 and 1024) followed by a finer divider (division by 1, 2, 3, 4, 5, 6, 7 or 8).

To calculate the needed frame frequency, the equation below must be used:

f_{frame} = \frac{f_{SLCK}}{(PRESC \cdot DIV \cdot NCOM)}

where:

f_SLCK = slow clock frequency
f_frame = frame frequency
PRESC = prescaler value (8, 16, 32, 64, 128, 256, 512 or 1024)
DIV = divider value (1, 2, 3, 4, 5, 6, 7, or 8)
NCOM = depends on the number of commons and is defined in the table below
Note: NCOM is automatically provided by the SLCDC.

For example, if SLCDC_MR.COMSEL is written to ‘0’ (1 common terminal on display device), the SLCDC introduces a divider by 16 so that NCOM = 16. If COMSEL is written to ‘3’ (3 common terminals on display device), the SLCDC introduces a divider by 5 so that the NCOM remains close to 16 (the frame rate is standardized regardless of the number of driven commons).

Table 36-3. NCOM
Number of Commons	NCOM	Divider
1	16	16
2	16	8
3	15	5
4	16	4
5	15	3
6	18	3
7	14	2
8	16	2