32.5.10 Transfer Status Register
| Name: | PERIPH_PTSR |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ERR | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXCBEN | RXCBEN | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXTEN | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXTEN | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 24 – ERR Transfer Bus Error
| Value | Description |
|---|---|
| 0 | PDC accesses are performed on valid memory address since the last write of ERRCLR bit in PERIPH_PTCR. |
| 1 | PDC transmit or receive pointer (or next pointer) is programmed with an invalid memory address since the last write of ERRCLR bit in PERIPH_PTCR. |
Bit 18 – TXCBEN Transmitter Circular Buffer Enable
| Value | Description |
|---|---|
| 0 | PDC Transmitter circular buffer mode is disabled. |
| 1 | PDC Transmitter circular buffer mode is enabled. |
Bit 16 – RXCBEN Receiver Circular Buffer Enable
| Value | Description |
|---|---|
| 0 | PDC Receiver circular buffer mode is disabled. |
| 1 | PDC Receiver circular buffer mode is enabled. |
Bit 8 – TXTEN Transmitter Transfer Enable
| Value | Description |
|---|---|
| 0 | PDC transmitter channel requests are disabled. |
| 1 | PDC transmitter channel requests are enabled. |
Bit 0 – RXTEN Receiver Transfer Enable
| Value | Description |
|---|---|
| 0 | PDC receiver channel requests are disabled. |
| 1 | PDC receiver channel requests are enabled. |