49.5.5 Optical Interface

To use the optical interface circuitry, the PLLA clock must be ready and programmed to generate a frequency within the range of 4096 up to 8192 kHz. This range allows a modulation by a clock with an adjustable frequency from 30 up to 60 kHz.

The optical interface is enabled by writing a ‘1’ to UART_MR.OPT_EN (see UART Mode Register).

When UART_MR.OPT_EN=1 or if UART_MR.ACON=1, the URXD pad is automatically configured in Analog mode and the analog comparator is enabled (see Optical Interface Block Diagram).

To match the characteristics of the off-chip optical receiver circuitry, the voltage reference threshold of the embedded comparator can be adjusted from VDD3V3/10 up to VDD/2 by programming UART_MR.OPT_CMPTH.

The NRZ output of the UART transmitter sub-module is modulated with the 30 up to 60 kHz modulation clock prior to driving the PIO controller.

A logical 0 on the UART transmitter sub-module output generates the said modulated signal (see Optical Interface Waveforms) having a frequency programmable from 30 kHz up to 60 kHz. 38 kHz is the default value assuming the PLLA clock frequency is 8192 kHz. A logical 1 on the UART transmitter sub-module output generates a stuck-at 1 output signal (no modulation). The idle polarity of the modulated signal is 1 ( UART_MR.OPT_MDINV = 0).

The idle polarity of the modulated signal can be inverted by writing a ‘1’ to UART_MR.OPT_MDINV.

The duty cycle of the modulated signal can be adjusted from 6.25% up to 50% (default value) by steps of 6.25% by programming UART_MR.OPT_DUTY.

If UART_MR.OPT_DMOD=1, the receive signal is demodulated. The duty cycle of the signal at the output of the analog comparator must be greater than 12%.

To reduce the power consumption of the optical link circuitry, the clock can be turned off and automatically turned on by the UART when activity occurs on receive line. This function is enabled only if UART_MR.OPT_WKUP=1.

When there is no further activity on the optical link (detected by example by a software timeout, etc.), the software stops the clock by writing a 1 in UART_CR.OPT_SLEEP. The clock of the UART is stopped and only the analog comparator must be enabled (UART_MR.ACON=1). As soon as a 1 is detected at the output of the analog comparator, the clock is immediately provided to the UART and the optical link is ready to receive and transmit.

The default configuration values of the optical link circuitries allow the 38 kHz modulation, a 50% duty cycle and an idle polarity, allowing a direct drive of an IR LED through a resistor.

Refer to the section “Electrical Characteristics” for drive capability of the buffer associated with the UTXD output.

In case of direct drive of the IR LED, the PIO must be programmed in Open-Drain mode.

If an off-chip current amplifier is used to drive the transmitting of the IR LED, the PIO must be programmed in Non Open-Drain drive mode for the line index driving the UTXD output, or in Open-Drain mode depending on the type of external circuitry.