1.6 Logic Doubling

“Logic Doubling” refers to the efficient and flexible CPLD architecture implemented across all ATF15XX devices. The ATF15XX family incorporates several features designed to improve connectivity and logic reusability, including:

• Increased availability of crosspoint multiplexers (MUXs) to support higher input node fan‑in
• Wider MUX channels feeding the Logic Array Blocks (LABs)
• Dual, independent feedback paths for each macrocell. The buried and pin-driver paths are split, allowing a register output to be buried while independently driving a combinatorial pin, or vice versa.
• Independent product‑term controlled output enable for every macrocell
• Selectable global clock polarity, supporting either rising or falling edge operation
• Global RESET functionality that can be logically combined (ORed) with a local product term