2.1.1 VHDL or Verilog Designs Using ProChip Designer®

For VHDL and Verilog designs, source files are compiled in ProChip Designer® to generate an EDIF netlist. After the EDIF file is created, users can access the Device Fitter properties window within ProChip Designer and configure settings under the Global Device, MC & I/O or Pins tab to define global, macrocell or pin-specific properties. To execute the fitter, users select the RunFitter button (as shown in Figure 2-1). This process generates both the Fitter Report file (.FIT) and the JEDEC programming file (.JED).