6.1 Hint 1 - Do Not Assign Pins

Although the fitter efficiently utilizes ATF15XX/ATF1500 device resources, poorly chosen pin and node assignments can prevent a design from fitting. The fitter employs multiple pin-assignment and logic-optimization strategies to map a design into the device. Global inputs are typically assigned to control pins, such as clock, reset or output enables, to reduce product-term usage in the macrocells. I/O pins are allocated to logic only after all foldback logic nodes and cascade logic resources in the macrocells have been fully utilized. As a result, the fitter attempts to optimize the maximum amount of logic into the fewest number of macrocells and selects pin assignments to reflect this. This process ensures that the logic is allocated for the best fit into the device. Poorly chosen pin assignments impose additional restrictions on the fitting process, forcing the fitter to tailor the logic around the pin assignments.