4.6 Signal/Design Placement

During the Signal/Design Placement step, the fitter places both pre-assigned and unassigned signals into the ATF15XX/ATF1500 device and maps the design logic using these signal placements. Pre-assigned signals are placed on the pins and nodes defined by the user, while unassigned signals are automatically placed by the fitter. Any nodes created by the fitter during the fitting process are also placed during this step.

After all signals are placed, the fitter evaluates the resources required to fit the design logic into the device and maps the design logic into the ATF15XX/ATF1500 architecture. During this mapping process, the fitter determines whether the logic is using invalid macrocell configurations, cannot fit into the available macrocells, uses incorrect register types or register control functions (i.e., Synchronous Preset) or uses too many resources in the device. If the design logic does not map into the ATF15XX/ATF1500 device, this step is repeated in a new design pass. If mapping fails during the last design pass, the fitter terminates the fitting process and reports that the design does not fit. If Signal/Design placement is successful in any design pass, the fuse-mapping process described in Fuse mapping will be performed.