4.4 Logic Optimization
After Global input pins are assigned, the fitter performs logic optimization to efficiently map the design logic into the ATF15XX/ATF1500 device. The logic optimization process flow is shown in Figure 4-5.
After Global input pins are assigned, the fitter performs logic optimization to efficiently map the design logic into the ATF15XX/ATF1500 device. The logic optimization process flow is shown in Figure 4-5.
DS20007127A
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