36.7.12 SPIxINTF
| Name: | SPIxINTF |
| Address: | 0x08A, 0x97 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRMTIF | TCZIF | SOSIF | EOSIF | RXOIF | TXUIF | ||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SRMTIF Shift Register Empty Interrupt Flag
| Value | Name | Description |
|---|---|---|
| x | Client | This bit is ignored |
| 1 | Host | The data transfer is complete |
| 0 | Host | Either no data transfers have occurred or a data transfer is in progress |
Bit 6 – TCZIF Transfer Counter is Zero Interrupt Flag
| Value | Description |
|---|---|
| 1 | The transfer counter has decremented to zero |
| 0 | No interrupt pending |
Bit 5 – SOSIF Start of Client Select Interrupt Flag
| Value | Description |
|---|---|
| 1 | SS_in transitioned from false to true |
| 0 | No interrupt pending |
Bit 4 – EOSIF End of Client Select Interrupt Flag
| Value | Description |
|---|---|
| 1 | SS_in transitioned from true to false |
| 0 | No interrupt pending |
Bit 2 – RXOIF Receiver Overflow Interrupt Flag
| Value | Description |
|---|---|
| 1 | Data
transfer completed when RXBF = 1 (edge-triggered) and RXR =
1 |
| 0 | No interrupt pending |
Bit 1 – TXUIF Transmitter Underflow Interrupt Flag
| Value | Description |
|---|---|
| 1 | Client
Data transfer started when TXBE = 1 and TXR =
1 |
| 0 | No interrupt pending |