36.7.11 SPIxINTE
| Name: | SPIxINTE |
| Address: | 0x08B, 0x98 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRMTIE | TCZIE | SOSIE | EOSIE | RXOIE | TXUIE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SRMTIE Shift Register Empty Interrupt Enable
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |
Bit 6 – TCZIE Transfer Counter is Zero Interrupt Enable
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |
Bit 5 – SOSIE Start of Client Select Interrupt Enable
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |
Bit 4 – EOSIE End of Client Select Interrupt Enable
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |
Bit 2 – RXOIE Receiver Overflow Interrupt Enable
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |
Bit 1 – TXUIE Transmitter Underflow Interrupt Enable
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |