6.1 Reset

The Reset block combines all Reset sources. It controls the device system’s Reset signal (SYSRST). The following is a list of device Reset sources:
  • MCLR: Master Clear Reset pin
  • SWR: Software Reset available through GestIC Library Loader
  • Power-on Reset (POR)
  • Brown-out Reset (BOR)
  • Watchdog Timer Reset (WDTR)

A simplified block diagram of the Reset block is illustrated in the following figure.

A pull-up resistor of 10 kΩ must be connected at all times to the MCLR pin.

Figure 6-2. System Reset Block Diagram

Timing Diagrams for POR and BOR are shown below:

Figure 6-3. Power-on Reset Timing
Note:
  1. The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN).
  2. Includes interval voltage regulator stabilization delay.
Figure 6-4. Brown-out Reset Timing