Host read is to receive gesture reports and command responses from the MGC3140. The timing diagram is shown below:Figure 7-2. I2C Host Read
Bit Timing Diagram
Address bits are latched into
the MGC3140 on the rising edges of SCL.
Data bits are latched out of
the MGC3140 on the rising edges of SCL.
ACK bit:
MGC3140 presents the ACK bit on the ninth clock
for address acknowledgment
I2C host
presents the ACK bit on the ninth clock for data acknowledgment
The I2C host must
monitor the SCL pin prior to asserting another clock pulse, as the MGC3140 may be holding off the I2C host by
stretching the clock.
I2C Communication
Steps
SCL and SDA lines are Idle high.
I2C host presents
Start bit to the MGC3140 by taking SDA high-to-low, followed
by taking SCL high-to-low.
I2C host presents
7-bit address, followed by a R/W = 1
(Read mode) bit to the MGC3140 on SDA, at the rising edge of
eight host clock (SCL) cycles.
MGC3140
compares the received address to its Device ID. If they match, the MGC3140 acknowledges (ACK) the host sent address by
presenting a low on SDA, followed by a low-high-low on SCL.
MGC3140 host monitors SCL,
as the MGC3140 may be clock-stretching, holding SCL low to
indicate that the I2C host should wait.
I2C host receives
eight data bits (MSB first) presented on SDA by the MGC3140,
at eight sequential I2C host clock (SCL) cycles. The data is latched
out on SCL falling edges to ensure it is valid during the subsequent SCL high
time.
If data transfer is not complete,
then:
I2C host
acknowledges (ACK) reception of the eight data bits by presenting a low
on SDA, followed by a low-high-low on SCL.
Go to Step 5.
If data transfer is complete,
then:
I2C host NACK’s reception of the
eight data bits and a completed data transfer by presenting a high on
SDA, followed by a low-high-low on SCL.
I2C Host Write Bit
Timing
I2C host write is to send supported commands to the MGC3140. The timing diagram is shown below:Figure 7-3. I2C Host Write
Bit Timing Diagram
Address bits are latched into the
MGC3140 on the rising edges of SCL.
Data bits are latched into the
MGC3140 on the rising edges of SCL.
ACK bit:
MGC3140 presents the ACK bit on the ninth clock for address
acknowledgment
MGC3140 presents the ACK bit on the ninth clock for data acknowledgment
The host must monitor the SCL pin
prior to asserting another clock pulse, as the MGC3140 may be
holding off the host by stretching the clock.
I2C Communication
Steps
SCL and SDA lines are Idle
high.
I2C host presents
Start bit to the MGC3140 by taking SDA high-to-low, followed
by taking SCL high-to-low.
I2C host presents
7-bit address, followed by a R/W = 0 (Write mode) bit to the
MGC3140 on SDA, at the rising edge of eight host clock
(SCL) cycles.
MGC3140
compares the received address to its Device ID. If they match, the MGC3140 acknowledges (ACK) the I2C host sent
address by presenting a low on SDA, followed by a low-high-low on SCL.
I2C host monitors SCL, as the MGC3140 may be clock stretching, holding SCL low to indicate
the I2C host should wait.
I2C host presents
eight data bits (MSB first) to the MGC3140 on SDA, at the
rising edge of eight host clock (SCL) cycles.
MGC3140
acknowledges (ACK) receipt of the eight data bits by presenting a low on SDA,
followed by a low-high-low on SCL.
If data transfer is not complete,
then go to Step 5.
Host presents a Stop bit to the
MGC3140 by taking SCL low-high, followed by taking SDA
low-to-high.
Important: The Stop condition after an
I2C data transmission is generated by the host controller after the data
transfer is completed. Thus, it is recommended to verify the number of bytes to be read
in the message header (Size field). Host must send the Stop condition as soon as the
exact number of bytes specified in the message header has been received. Failing to do
so may result in abnormal interface operation.
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