7.2.5 System Pin List

Table 7-5. System Pin Description
Pin No.	Pin Name	Power Rail	I/O Type	Description
114	MIPI_D0_N	VDD_2V5	DPHYIO	MIPI DPHY negative differential output data lane 0
113	MIPI_D0_P	VDD_2V5	DPHYIO	MIPI DPHY positive differential output data lane 0
112	MIPI_D1_N	VDD_2V5	DPHYIO	MIPI DPHY negative differential output data lane 1
111	MIPI_D1_P	VDD_2V5	DPHYIO	MIPI DPHY positive differential output data lane 1
110	MIPI_D2_N	VDD_2V5	DPHYIO	MIPI DPHY negative differential output data lane 2
109	MIPI_D2_P	VDD_2V5	DPHYIO	MIPI DPHY positive differential output data lane 2
108	MIPI_D3_N	VDD_2V5	DPHYIO	MIPI DPHY negative differential output data lane 3
107	MIPI_D3_P	VDD_2V5	DPHYIO	MIPI DPHY positive differential output data lane 3
116	MIPI_CK_N	VDD_2V5	DPHYIO	MIPI DPHY negative differential output clock lane
115	MIPI_CK_P	VDD_2V5	DPHYIO	MIPI DPHY positive differential output clock lane
123	USBA_P	VDD_3V3	USBHS	USB host port A high-speed data +
122	USBA_N	VDD_3V3	USBHS	USB host port A high-speed data -
121	USBB_P	VDD_3V3	USBHS	USB host port B high-speed data +
120	USBB_N	VDD_3V3	USBHS	USB host port B high-speed data -
119	USBC_P	VDD_3V3	USBHS	USB host port C high-speed data +
118	USBC_N	VDD_3V3	USBHS	USB host port C high-speed data -
125	AUDIO_CLK	VDD_3V3	CLOCK	Audio clock output
78	WKUP0	VDDBU	SYSC	Wake-up input. 100kΩ Internal Pull-Up.
79	SHDN	VDDBU	SYSC	Shutdown control
151	JTAGSEL	VDDBU	SYSC	JTAG selection
147	JTAG_TCK	VDD_3V3	RSTJTAG	Test clock
148	JTAG_TDI	VDD_3V3	RSTJTAG	Test data in
152	JTAG_TDO	VDD_3V3	RSTJTAG	Test data out
149	JTAG_TMS	VDD_3V3	RSTJTAG	Test mode select
150	JTAG_RTCK	VDD_3V3	RSTJTAG	Return test clock
77	nRST	VDD_3V3	RSTJTAG	External nReset input/output. 10kΩ internal pull-up.
17	NAND_CS_IN	VDD_3V3	GPIO	NAND Flash chip select input. 100kΩ internal pull-up.
19	NAND_WP	VDD_3V3	GPIO	NAND Flash write protect. 100kΩ internal pull-up.
31	TXRXA_P	AVDDL	Analog	Physical receive or transmit signal (+ differential)
32	TXRXA_N	AVDDL	Analog	Physical receive or transmit signal (– differential)
33	TXRXB_P	AVDDL	Analog	Physical receive or transmit signal (+ differential)
34	TXRXB_N	AVDDL	Analog	Physical receive or transmit signal (– differential)
35	TXRXC_P	AVDDL	Analog	Physical receive or transmit signal (+ differential)
36	TXRXC_N	AVDDL	Analog	Physical receive or transmit signal (– differential)
37	TXRXD_P	AVDDL	Analog	Physical receive or transmit signal (+ differential)
38	TXRXD_N	AVDDL	Analog	Physical receive or transmit signal (– differential)
44	GMAC_LED5_ALLPHYAD	VDD_3V3	GPIO	Programmable LED5 output/PHY address strap pin
45	GMAC_LED4_MAGJACK	VDD_3V3	GPIO	Programmable LED4 output/MagJack register settings. 10kΩ internal pull-up.
46	GMAC_LED3_PHYAD2	VDD_3V3	GPIO	Programmable LED3 output/PHYAD2
47	GMAC_LED2_PHYAD1	VDD_3V3	GPIO	Programmable LED2 output/PHYAD1
48	GMAC_LED1_PHYAD0	VDD_3V3	GPIO	Programmable LED1 output/PHYAD0
43	GMAC_NRST	VDD_3V3	GPIO	Gigabit PHY reset line. 10kΩ internal pull-up.
21	QSPI_CS_IN	VDD_3V3	GPIO	NOR Flash chip select input. 10kΩ internal pull-up.
22	125MHz_EN	VDD_3V3	GPIO	125-MHz clock generation enable input (Enable high)

114

MIPI_D0_N

VDD_2V5

DPHYIO

MIPI DPHY negative differential output data lane 0

113

MIPI_D0_P

VDD_2V5

DPHYIO

MIPI DPHY positive differential output data lane 0

112

MIPI_D1_N

VDD_2V5

DPHYIO

MIPI DPHY negative differential output data lane 1

111

MIPI_D1_P

VDD_2V5

DPHYIO

MIPI DPHY positive differential output data lane 1

110

MIPI_D2_N

VDD_2V5

DPHYIO

MIPI DPHY negative differential output data lane 2

109

MIPI_D2_P

VDD_2V5

DPHYIO

MIPI DPHY positive differential output data lane 2

108

MIPI_D3_N

VDD_2V5

DPHYIO

MIPI DPHY negative differential output data lane 3

107

MIPI_D3_P

VDD_2V5

DPHYIO

MIPI DPHY positive differential output data lane 3

116

MIPI_CK_N

VDD_2V5

DPHYIO

MIPI DPHY negative differential output clock lane

115

MIPI_CK_P

VDD_2V5

DPHYIO

MIPI DPHY positive differential output clock lane

123

USBA_P

VDD_3V3

USBHS

USB host port A high-speed data +

122

USBA_N

VDD_3V3

USBHS

USB host port A high-speed data -

121

USBB_P

VDD_3V3

USBHS

USB host port B high-speed data +

120

USBB_N

VDD_3V3

USBHS

USB host port B high-speed data -

119

USBC_P

VDD_3V3

USBHS

USB host port C high-speed data +

118

USBC_N

VDD_3V3

USBHS

USB host port C high-speed data -

125

AUDIO_CLK

VDD_3V3

CLOCK

Audio clock output

78

WKUP0

VDDBU

SYSC

Wake-up input. 100kΩ Internal Pull-Up.

79

SHDN

VDDBU

SYSC

Shutdown control

151

JTAGSEL

VDDBU

SYSC

JTAG selection

147

JTAG_TCK

VDD_3V3

RSTJTAG

Test clock

148

JTAG_TDI

VDD_3V3

RSTJTAG

Test data in

152

JTAG_TDO

VDD_3V3

RSTJTAG

Test data out

149

JTAG_TMS

VDD_3V3

RSTJTAG

Test mode select

150

JTAG_RTCK

VDD_3V3

RSTJTAG

Return test clock

77

nRST

VDD_3V3

RSTJTAG

External nReset input/output. 10kΩ internal pull-up.

17

NAND_CS_IN

VDD_3V3

GPIO

NAND Flash chip select input. 100kΩ internal pull-up.

19

NAND_WP

VDD_3V3

GPIO

NAND Flash write protect. 100kΩ internal pull-up.

31

TXRXA_P

AVDDL

Analog

Physical receive or transmit signal (+ differential)

32

TXRXA_N

AVDDL

Analog

Physical receive or transmit signal (– differential)

33

TXRXB_P

AVDDL

Analog

Physical receive or transmit signal (+ differential)

34

TXRXB_N

AVDDL

Analog

Physical receive or transmit signal (– differential)

35

TXRXC_P

AVDDL

Analog

Physical receive or transmit signal (+ differential)

36

TXRXC_N

AVDDL

Analog

Physical receive or transmit signal (– differential)

37

TXRXD_P

AVDDL

Analog

Physical receive or transmit signal (+ differential)

38

TXRXD_N

AVDDL

Analog

Physical receive or transmit signal (– differential)

44

GMAC_LED5_ALLPHYAD

VDD_3V3

GPIO

Programmable LED5 output/PHY address strap pin

45

GMAC_LED4_MAGJACK

VDD_3V3

GPIO

Programmable LED4 output/MagJack register settings. 10kΩ internal pull-up.

46

GMAC_LED3_PHYAD2

VDD_3V3

GPIO

Programmable LED3 output/PHYAD2

47

GMAC_LED2_PHYAD1

VDD_3V3

GPIO

Programmable LED2 output/PHYAD1

48

GMAC_LED1_PHYAD0

VDD_3V3

GPIO

Programmable LED1 output/PHYAD0

43

GMAC_NRST

VDD_3V3

GPIO

Gigabit PHY reset line. 10kΩ internal pull-up.

21

QSPI_CS_IN

VDD_3V3

GPIO

NOR Flash chip select input. 10kΩ internal pull-up.

22

125MHz_EN

VDD_3V3

GPIO

125-MHz clock generation enable input (Enable high)