45.8.6 Reference Control
| Name: | REFCTRL |
| Offset: | 0x08 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REFCOMP | REFSEL[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable
The gain error can be reduced by enabling the reference buffer offset compensation. This will increase the start-up time of the reference.
| Value | Description |
|---|---|
| 0 | Reference buffer offset compensation is disabled. |
| 1 | Reference buffer offset compensation is enabled. |
Bits 3:0 – REFSEL[3:0] Reference Selection
These bits select the reference for the ADC.
| Value | Name | Description |
|---|---|---|
| 0x0 | INTREF | internal bandgap reference, refer to the VREF.SEL bit-field in SUPC-Supply Controller for more details |
| x01 | Reserved | |
| 0x2 | INTVCC0 | 1/2 VDDANA (only for VDDANA > 2.0v) |
| 0x3 | INTVCC1 | VDDANA |
| 0x4 | AREFA | External reference |
| 0x5 | AREFB | External reference |
| 0x6 | AREFC | External reference (ADC1 only) |
| other | - | Reserved |