55.5.5 Fractional Digital Phase Lock Loop (FDPLL) Characteristics (105°C)

Table 55-26. Fractional Digital Phase Lock Loop Characteristics (2)
SymbolParameterConditionsMin.Typ.Max.Units
Jp Period jitter (Peak-Peak value)fIN = 32 kHz, fOUT = 96 MHz -1.9 2.9%
fIN = 32 kHz, fOUT = 200 MHz -3.4 5.6
fIN = 3.2 MHz, fOUT = 96 MHz -2.0 3.1
fIN = 3.2 MHz, fOUT = 200 MHz -4.3 7.1
Duty (1)Duty cycle --50-%
Note:
  1. These are based on simulation. These values are not covered by test or characterization.
  2. These FDPLL200Mn characteristics are applicable with LDO regulator and a direct reference (i.e., REFCLK is XOSC or XOSC32K, not GCLK).
Table 55-27. Fractional Digital Phase Lock Loop Power Consumption
SymbolParameterConditionsTATyp.Max.Units
IDDCurrent Consumption Ck = 96 MHz, VDD = 3.3VMax. 105°C

Typ. 25°C

0.91.8mA
Ck = 200 MHz, VDD = 3.3V2.02.6