37.8.7 Interrupt Enable Set
| Name: | INTENSET |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INSTREND | CSRISE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | TXC | DRE | RXC | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 10 – INSTREND Instruction End Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' will set the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The INSTREND interrupt is disabled. |
| 1 | The INSTREND interrupt is enabled. |
Bit 8 – CSRISE Chip Select Rise Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' will set the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The CSRISE interrupt is disabled. |
| 1 | The CSRISE interrupt is enabled. |
Bit 3 – ERROR Overrun Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' will set the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The ERROR interrupt is disabled. |
| 1 | The ERROR interrupt is enabled. |
Bit 2 – TXC Transmission Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' will set the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The TXC interrupt is disabled. |
| 1 | The TXC interrupt is enabled. |
Bit 1 – DRE Transmit Data Register Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' will set the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The DRE interrupt is disabled. |
| 1 | The DRE interrupt is enabled. |
Bit 0 – RXC Receive Data Register Full Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' will set the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The RXC interrupt is disabled. |
| 1 | The RXC interrupt is enabled. |