37.8.3 Baud Rate


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	DLYBS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BAUD[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
							CPHA	CPOL
Access							R/W	R/W
Reset							0	0

Bits 23:16 – DLYBS[7:0] Delay Before SCK

This field defines the delay from CS valid to the first valid SCK transition.

When DLYBS equals zero, the CS valid to SCK transition is 1/2 the SCK clock period.

Otherwise, the following equation determines the delay:

Equation 37-2. Delay Before SCK

D e l a y B e f o r e S C K = \frac{D L Y B S}{M C K}

Bits 15:8 – BAUD[7:0] Serial Clock Baud Rate

The QSPI uses a modulus counter to derive the SCK baud rate from the module clock CLK_QSPI_AHB. The Baud rate is selected by writing a value from 0 to 255 in the BAUD field. The following equation determines the SCK baud rate:

Equation 37-1. SCK Baud Rate

S C K B a u d R a t e = \frac{M C K}{(B A U D + 1)}

Bit 1 – CPHA Clock Phase

CPHA determines which edge of SCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between Host and Client devices.

Value	Description
0	Data is captured on the leading edge of SCK and changed on the following edge of SCK.
1	Data is changed on the leading edge of SCK and captured on the following edge of SCK.

Bit 0 – CPOL Clock Polarity

CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to produce the required clock/data relationship between Host and Client devices.

Value	Description
0	The inactive state value of SCK is logic level zero.
0	The inactive state value of SCK is logic level 'one'.

Name:	BAUD
Offset:	0x08
Reset:	0x00000000
Property:	PAC Write-Protection