25.6.2 Memory Organization

Memory space is divided as follows:

• The main address space where 2 physical NVM banks (BANKA and BANKB) are mapped.
• The auxiliary space which contains:
  • The user page (USER)
  • The calibration page (CB)
  • Factory and signature pages (FS)

The BANKA and BANKB can be swapped in the address space. For additional information, refer to the Memory Bank Swapping.

Refer to the Physical Memory Map for memory sizes and addresses for each device.

The BANKA, BANKB and AUX pages have different erase and write granularities, as provided in the table below.

The NVM is organized into two banks, each bank is organized into blocks, where each block contains sixteen pages and page size is 512 bytes.

The lower blocks in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT fuses, and the upper rows can be allocated to SmartEEPROM.

The NVM memory is separated into six parts:

• CB space: Contains factory calibration and system configuration information.
  • Address; 0x00800000
  • Size: 1 page
  • Property: Read-Only
• FS space: Contains the factory signature information.
  • Address; 0x00806000
  • Size: 4 pages
  • Property: Read-Only.
• USER space: Contains user-defined startup configuration. The first word is reserved, and used during the NVMCTRL start-up to automatically configure the device.
  • Address: 0x00804000
  • Size: 1 page
  • Property: Read-Write
• Main address space: Divided into 32 equal size regions. Each region can be protected against write or erase operation. The 32-bit RUNLOCK register reflects the protection of each region. This register is automatically updated after power-up with the region lock user fuse data found in the NVM LOCKS field, refer to the Chapter Memories. To lock or unlock a region, the Lock Region (LR) or Unlock Regions (UR) commands can be issued.
  • Address: 0x00000000
  • Size: PARAM.NVMP pages.
  • Property: Read-Write
• Bootloader space

  The bootloader section starts at the beginning of the main address space; Its size is defined by the NVM User Row BOOTPROT[3:0] fuse. It is protected against write or erase operations, except if STATUS.BPDIS is set. Issuing a write or erase command at an address inside the BOOTPROT section sets STATUS.PROGE and STATUS.LOCKE. STATUS.BPDIS can be set by issuing the Set BOOTPROT Disable command (SBPDIS). It is cleared by issuing the Clear BOOTPROT Disable command (CBPDIS). This allows to program a new bootloader without changing the user page and issuing a new NVMCTRL startup sequence to reload the user configuration. The BOOTPROT section is not erased during a Chip-Erase operation even if STATUS.BPDIS is high.

  • Address: 0x00000000
  • Size: (15 - STATUS.BOOTPROT) × 8192
  • Property: Read-Only.
• SmartEEPROM raw data space: The SmartEEPROM algorithm emulates an EEPROM with a portion of the NVM main. SmartEEPROM raw data is mapped at the end of the main address space. SmartEEPROM allocated space in the main address space is not accessible from AHB0/1. Any AHB access throws a Hardfault exception. Any command issued with ADDR pointing in the SmartEEPPROM space is discarded, INTFLAG.DONE and INTFLAG.ADDRE are set in this case.
  • Address: PARAM.NVMP*512-2*SEESTAT.SBLK*8192
  • Size: 2*SEESTAT.SBLK*8192
  • Property: Not readable, not writable

Each section has a different protection status, as provided in the table below.