28.6.5 Digital Phase Locked Loop (FDPLL200Mn) Operation

The task of the DPLL is to maintain coherence between the input (reference) signal and the respective output frequency CLK_DPLL through phase comparison. The DPLL controller supports four independent sources of reference clocks:

  • XOSC32K: This clock is provided by the 32K External Crystal Oscillator (XOSC32K).
  • XOSC0 and XOSC1: These clocks are provided by the External Multipurpose Crystal Oscillator (XOSC).
  • GCLK: This clock is provided by the Generic Clock Controller.

When the controller is enabled, the relationship between the reference clock frequency and the output clock frequency is as shown below:

f CLK_DPLLn = f CKR × ( LDR + 1 + LDRFRAC 32 )

Where:

fCLK_DPLLn is the frequency of the DPLLn output clock, LDR is the loop divider ratio integer part and LDRFRAC is the loop divider ratio fractional part, fCKR is the frequency of the selected reference clock.

Figure 28-2. DPLLn Block Diagram

When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in the DPLL Ratio register (DPLLnRATIO.LDRFRAC) is zero, the DPLL works in Integer mode. Otherwise, the fractional mode is activated. The fractional part has a negative impact on the jitter of the DPLL.

For example (Integer mode only): Assuming fCKR = 32 kHz and fCLK_DPLLn = 112 MHz, the multiplication ratio is 3500. It means that LDR must be set to 3499.

For example (Fractional mode): Assuming fCKR = 32 kHz and fCLK_DPPLn = 112.003000 MHz, the multiplication ratio is 3500.9375 (3500 + 3/32). Thus LDR is set to 3499 and LDRFRAC to 3.