28.6.5.1 Basic Operation

Initialization, Enabling, Disabling, and Resetting

The DPLLn is enabled by writing a ‘1’ to the Enable bit in the Control register (DPLLnCTRLA.ENABLE). The DPLLn is disabled by writing a ‘0’ to DPLLnCTRLA.ENABLE. The DPLLnSYNCBUSY.ENABLE is set when the DPLLnCTRLA.ENABLE bit is modified. It is cleared when the DPLLn output clock CLK_DPLLn has sampled the bit at the high level, or cleared when the output clock is no longer running (for disable operation).

Figure 28-3. Enable Synchronization Busy Operation

The frequency of the DPLLn output clock CLK_DPLLn is stable when the module is enabled and when the LOCK bit is set. When DPLLnCTRLB.LTIME is different from 0, a user defined lock time is used to validate the lock operation. In that case the lock time is constant. If DPLLnCTRLB.LTIME is zero, the lock signal is linked with the status bit of the DPLLn (DPLLnSTATUS.LOCK), the lock time vary depending on the filter selection and final target frequency. When DPLLnCTRLB.WUF is set the wake up fast mode is activated. In that mode the clock gating cell is enabled at the end of the startup time. At that time the final frequency is not stable as it is still the acquisition period, but it allows to save hundreds of microseconds. After the first acquisition, DPLLnCTRLB.LBYPASS indicates if the Lock signal is discarded from the control of the clock gater (CG) generating the output clock CLK_DPLLn.

Table 28-3. CLK_DPLLn Behavior from Startup to First Edge Detection.
WUF	LTIME	CLK_DPLLn Behavior
0	0	Normal Mode: First Edge when lock is asserted
0	Not Equal To Zero	Lock Timer Timeout mode: First Edge when the timer down-counts to 0.
1	X	Wake Up Fast Mode: First Edge when CK is active (startup time)

Table 28-4. CLK_DPLLn Behavior after First Edge Detection.
LBYPASS	CLK_DPLLn Behavior
0	Normal Mode: the CLK_DPLLn is turned off when lock signal is low.
1	Lock Bypass Mode: the CLK_DPLLn is always running, lock is irrelevant.

Figure 28-4. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode

Figure 28-5. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode when Wakeup Fast is Activated

Figure 28-6. CK and CLK_DPLL Output from Running Mode to DPLLC Off Mode.

Operating Modes

The DPLLn will behave differently in different sleep modes based on the settings of DPLLnCTRLA.RUNSTDBY, DPLLnCTRLA.ONDEMAND and DPLLnCTRLA.ENABLE.

Table 28-5. DPLL Sleep Behavior
DPLLCTRLA.RUNSTDBY	DPLLCTRLA.ONDEMAND	DPLLCTRLA.ENABLE	Sleep Behavior
-	-	0	Disabled
0	0	1	Always run in Idle Sleep modes. Run in Standby Sleep mode if requested by a peripheral.
0	1	1	Only run in Idle or Standby Sleep modes if requested by a peripheral.
1	0	1	Always run in Idle and Standby Sleep modes.
1	1	1	Only run in Idle or Standby Sleep modes if requested by a peripheral.

Reference Clock Switching

When a software operation requires reference clock switching, the normal operation is to disable the DPLLn, modify the DPLLnCTRLB.REFCLK to select the desired reference source and activate the DPLLn again. The CLK_DPLLn output clock is ready when DPLLnSTATUS.CLKRDY bit is set.

XOSC Reference Clock Divider

DPLLnCTRLB.DIV[10:0] bits are used to set the XOSC clock division factor and can be calculated with following formula:

f_{DIV} = \frac{f XOSC}{2 \times (DIV + 1)}

For more information, refer to DPLLnCTRLB.

Loop Divider Ratio Updates

The DPLLn Controller supports on-the-fly update of the DPLLnRATIO register, so it is allowed to modify the loop divider ratio and the loop divider ratio fractional part when the DPLLn is enabled. Ensure the following conditions, or else the on-the-fly updating of the divider ratio will fail:

DPLLnCTRLB.LBYPASS must be '0' (normal mode).
DPLLnCTRLB.LTIME must not be 0x0, which is the default value.
A DPLLn 32KHz clock (GCLK_DPLLn_32K) is configured in the GCLK peripheral as the internal lock timer.

Write DPLLnRATIO.LDR[12:0] bits to set the integer part of the frequency multiplier, and write DPLLnRATIO.LDRFRAC[4:0] bits to set the fractional part of the frequency multiplier. Due to synchronization there is a delay between writing to DPLLnRATIO.LDRFRAC[4:0] or DPLLnRATIO.LDR[12:0] and the effect on the DPLLn output clock. The value written DPLLnRATIO.LDRFAC[4:0] or DPLLnRATIO.LDR[12:0] will be read back immediately, and the DPLLRATIO bit in the synchronization busy register DPLLnSYNCBUSY.DPLLRATIO, will be set. DPLLnSYNCBUSY.DPLLRATIO will be cleared when the operation is completed.STATUS.DPLLnLDRTO is set when the DPLLnRATIO register has been modified and the DPLLn analog cell has successfully sampled the updated value. At that time the DPLLnSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a stable state. Note that if only the fractional part of loop divider ratio (DPLLnRATIO.LDRFRAC) is updated, the lock status (DPLLnSTATUS.LOCK) will not be cleared.

Figure 28-7. RATIOCTRL Register Update Operation

Digital Filter Selection

The digital filter selection can be changed from the filter selection register DPLLnCTRLB.FILTER. The DPLL digital filter coefficients are automatically adjusted in order to provide a good compromise between stability and jitter. For more information, refer to DPLLnCTRLB.

Sigma-Delta DCO Filter Selection

The sigma-delta DAC low pass filter can be controlled and adjusted from the DCO filter selection register DPLLnCTRLB.DCOFILTER[2:0]. For more information, refer to DPLLnCTRLB.