24.9.10 GMAC Interrupt Status Register

This register indicates the source of the interrupt. An interrupt source must be enabled in the mask register first so the corresponding bits of this register will be set and the GMAC interrupt signal will be asserted in the system.

Name:	ISR
Offset:	0x024
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
			TSUCMP	WOL	RXLPISBC	SRI	PDRSFT	PDRQFT
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	PDRSFR	PDRQFR	SFT	DRQFT	SFR	DRQFR
Access	R	R	R	R	R	R
Reset	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
		PFTR	PTZ	PFNZ	HRESP	ROVR
Access		R	R	R	R	R
Reset		0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TCOMP	TFC	RLEX	TUR	TXUBR	RXUBR	RCOMP	MFS
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 29 – TSUCMP TSU Timer Comparison

Indicates TSU times count and comparison value are equal.

Bit 28 – WOL Wake On LAN

WOL interrupt. Indicates a WOL message has been received.

Bit 27 – RXLPISBC Receive LPI indication Status Bit Change

Receive LPI indication status bit change.

Cleared on read.

Bit 26 – SRI TSU Seconds Register Increment

Indicates the register has incremented.

Cleared on read.

Bit 25 – PDRSFT PDelay Response Frame Transmitted

Indicates a PTP pdelay_resp frame has been transmitted.

Cleared on read.

Bit 24 – PDRQFT PDelay Request Frame Transmitted

Indicates a PTP pdelay_req frame has been transmitted.

Cleared on read.

Bit 23 – PDRSFR PDelay Response Frame Received

Indicates a PTP pdelay_resp frame has been received.

Cleared on read.

Bit 22 – PDRQFR PDelay Request Frame Received

Indicates a PTP pdelay_req frame has been received.

Cleared on read.

Bit 21 – SFT PTP Sync Frame Transmitted

Indicates a PTP sync frame has been transmitted.

Cleared on read.

Bit 20 – DRQFT PTP Delay Request Frame Transmitted

Indicates a PTP delay_req frame has been transmitted.

Cleared on read.

Bit 19 – SFR PTP Sync Frame Received

Indicates a PTP sync frame has been received.

Cleared on read.

Bit 18 – DRQFR PTP Delay Request Frame Received

Indicates a PTP delay_req frame has been received.

Cleared on read.

Bit 14 – PFTR Pause Frame Transmitted

Indicates a pause frame has been successfully transmitted after being initiated from the Network Control Register.

Cleared on read.

Bit 13 – PTZ Pause Time Zero

Set when either the Pause Time Register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field.

Cleared on read.

Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received

Indicates a valid pause has been received that has a non-zero pause quantum field.

Cleared on read.

Bit 11 – HRESP HRESP Not OK

Set when the DMA block sees HRESP not OK.

Cleared on read.

Bit 10 – ROVR Receive Overrun

Set when the receive overrun status bit is set.

Cleared on read.

Bit 7 – TCOMP Transmit Complete

Set when a frame has been transmitted.

Cleared on read.

Bit 6 – TFC Transmit Frame Corruption Due to AHB Error

Transmit frame corruption due to AHB error. Set if an error occurs during reading a transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame.

Bit 5 – RLEX Retry Limit Exceeded

Retry Limit Exceeded Transmit error.

Cleared on read.

Bit 4 – TUR Transmit Underrun

This interrupt is set if the transmitter was forced to terminate an ongoing frame transmission due to further data being unavailable.

This interrupt is also set if a transmitter status write back has not completed when another status write back is attempted.

This interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because the used bit was read.