24.9.13 GMAC Interrupt Mask Register
This register is a read-only register indicating which interrupts are masked. All bits are set at Reset and can be reset individually by writing to the Interrupt Enable Register (IER), or set individually by writing to the Interrupt Disable Register (IDR).
For test purposes there is a write-only function to this register that allows the bits in the Interrupt Status Register to be set or cleared, regardless of the state of the mask register. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written.
The following values are valid for all listed bit names of this register when read:
0: The corresponding interrupt is enabled.
1: The corresponding interrupt is not enabled.
| Name: | IMR |
| Offset: | 0x030 |
| Reset: | 0x3FFFFFFF |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TSUCMP | WOL | RXLPISBC | SRI | PDRSFT | PDRQFT | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PDRSFR | PDRQFR | SFT | DRQFT | SFR | DRQFR | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXINT | PFTR | PTZ | PFNZ | HRESP | ROVR | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMP | TFC | RLEX | TUR | TXUBR | RXUBR | RCOMP | MFS | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 29 – TSUCMP TSU Timer Comparison
Bit 28 – WOL Wake On LAN
WOL interrupt. Indicates a WOL message has been received.
Bit 27 – RXLPISBC Enable RX LPI Indication
Bit 26 – SRI TSU Seconds Register Increment
Indicates the register has incremented.
Cleared on read.