47.6.4 DMA Operation

In single mode (CTRLB.DIFF=0), DAC Controller generates the following DMA requests:

• Data Buffer 0 Empty (EMPTY0): The request is set when data is transferred from DATABUF0 or DATA0 to the internal data buffer of DAC0. The request is cleared when either DATA0 register or DATABUF0 register is written, or by writing a '1' to the EMPTY0 bit in the Interrupt Flag register (INTFLAG.EMPTY0).
• Data Buffer 1 Empty (EMPTY1): The request is set when data is transferred from DATABUF1 or DATA1 to the internal data buffer of DAC1. The request is cleared when either DATA0 register or DATABUF1 register is written, or by writing a one to the EMPTY1 bit in the Interrupt Flag register (INTFLAG.EMPTY1).
• Filter 0 Result Ready (RESRDY0): The request is set when the filter is used as standalone, and filter output is ready. The request is cleared by writing a '1' to the RESRDY0 bit in the Interrupt Flag register (INTFLAG.RESRDY0).
• Filter 1 Result Ready (RESRDY1): The request is set when the filter is used as standalone, and filter output is ready. The request is cleared by writing a '1' to the RESRDY1 bit in the Interrupt Flag register (INTFLAG.RESRDY1).

In differential mode (CTRLB.DIFF=1), DAC Controller generates the following DMA request:

• Data Buffer 0 Empty (EMPTY0): The request is set when data is transferred from DATABUF0 or DATA0 to the internal data buffer of DAC1. The request is cleared when either DATA0 register or DATABUF0 register is written, or by writing a one to the EMPTY0 bit in the Interrupt Flag register (INTFLAG.EMPTY0).

If the CPU accesses the registers which are source of DMA request set/clear condition, the DMA request can be lost or the DMA transfer can be corrupted, if enabled.