22.8.11 Busy Channels

Name:	BUSYCH
Offset:	0x28
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	BUSYCH31	BUSYCH30	BUSYCH29	BUSYCH28	BUSYCH27	BUSYCH26	BUSYCH25	BUSYCH24
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	BUSYCH23	BUSYCH22	BUSYCH21	BUSYCH20	BUSYCH19	BUSYCH18	BUSYCH17	BUSYCH16
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BUSYCH15	BUSYCH14	BUSYCH13	BUSYCH12	BUSYCH11	BUSYCH10	BUSYCH9	BUSYCH8
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	BUSYCH7	BUSYCH6	BUSYCH5	BUSYCH4	BUSYCH3	BUSYCH2	BUSYCH1	BUSYCH0
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – BUSYCHn Busy Channel n [x=31..0]

This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled.

This bit is set when DMA channel n starts a DMA transfer.