9.3 SRAM Memory Configuration

Retention

Depending on the application and power budget needs, part of the system memory can be retained in Standby or Hibernate sleep modes. The amount of the SRAM retained in this mode is software selectable, by writing the RAMCFG bits in the Power Manager Standby Configuration register and Hibernate Configuration register respectively (STDBYCFG.RAMCFG and HIBCFG.RAMCFG).

By default, the entire system memory section is retained, but no retention or bottom 32KB memory retention options are also available.

RAM Error Correction

For safety applications, the SAM D5x/E5x family embeds error correction codes (ECC) to detect and correct single bit errors, or to enable dual error detection for the system memory. The ECC is software selectable through the RAM ECCDIS bit in the NVM User Row. For additional information, refer to Table 9-2.

When enabled, the top half system memory will be reserved to store the ECC, and will not be available for the application.

CoreSight ETB Connection

When enabled, the bottom 32 KB system memory space is reserved for CoreSight ETB debug usage. The figure below shows an example where both ECC and CoreSight ETB are enabled.