This section provides details on pin diagrams and pinout table of the RNWF11 Module.Figure 2-2. RNWF11 Module Pin Diagram
Table 2-1. RNWF11 Module Pinout Table
Pin Number
Pin Name
Pin Type
Pin Description
1
GND
P
Ground
2
AN4
I
Analog input 4
CVD4
O
Touch 4
PB4
I/O
Port B digital I/O 4
3
OC2
O
Output compare 2
4
Reserved
—
Reserved, Do not connect
5
Reserved
—
Reserved, Do not connect
6
Reserved
—
Reserved, Do not connect
7
OC3
O
Output compare 3
8
ETXEN
O
Ethernet transmit enable output
PC13
I/O
Port C digital I/O 13
9
ERXD0
I
Ethernet RMII receive data bit 0
PC11
I/O
Port C digital I/O 11
10
ERXD1
I
Ethernet RMII receive data bit 1
PC10
I/O
Port C digital I/O 10
11
GND
P
Ground
12
ETH_CLK_OUT
O
Ethernet RMII reference clock out (50 MHz), requires an external 33Ω series termination resistor
PC12
I/O
Port C digital I/O 12
13
ETXD1
O
Ethernet RMII transmit data bit 1
PC14
I/O
Port C digital I/O 14
14
ETXD0
I
Ethernet RMII transmit data bit 0
PC15
I/O
Port C digital I/O 15
15
ERXDV
I
Ethernet RMII receive data valid
PK12
I/O
Port K digital I/O 12
16
EMDIO
I/O
Ethernet management data I/O
PK13
I/O
Port K digital I/O 13
17
EMDC
O
Ethernet management data clock
PK14
I/O
Port K digital I/O 14
18
ERXERR
I
Ethernet RMII receive error
PC9
I/O
Port C digital I/O 9
19
SDI1
I
SPI data in
PC7
I/O
Port C digital I/O 7
20
SPI1CS
O
SPI clock select (active-low)
PA1
I/O
Port A digital I/O 1
21
SCK1
O
SPI clock
PC6
I/O
Port C digital I/O 6
22
GND
P
Ground
23
SDO1
O
SPI data out
PC8
I/O
Port C digital I/O 8
24
BT_CLK_OUT
O
Bluetooth® reference clock out (26 MHz)
PK4
I/O
Port K Digital I/O 4
25
PTA_BT_PRIO
I/O
Packet Traffic Arbitration (PTA) Bluetooth priority signal for Bluetooth and Wi-Fi® coexistence
PK6
I/O
Port K digital I/O 6
26
MCLR
I
Master Clear (Reset, Active low, Requires external RC circuit)
27
PTA_WLAN_ACTIVE
I/O
PTA Wi-Fi active signal for Bluetooth and Wi-Fi coexistence
PK5
I/O
Port K digital I/O 5
28
PTA_BT_ACTIVE
I/O
PTA Wi-Fi active signal for Bluetooth and Wi-Fi coexistence
PK7
I/O
Port K digital I/O 7
29
U1TX
O
UART 1 transmit for host interface
30
U1RX
I
UART 1 receive for host interface
31
GND
P
Ground
32
SDA1
I/O
I2C data to ATECC608B TrustFlex
PA5
I/O
Port A digital I/O 5
33
SCL1
I/O
I2C clock to ATECC608B TrustFlex
PA4
I/O
Port A digital I/O 4
34
RMII_Enable
O
Ethernet RMII enable
PK1
I/O
Port K digital I/O 1
35
U2TX
O
UART 2 TX used as debug UART TX
36
GND
P
Ground
37
GND
P
Ground
38
NC
—
Do not connect
39
GND
P
Ground
40
GND
P
Ground
41
AN17
I
Analog input 17
PA10
I/O
Port A digital I/O 10
WAKE
I
Wake input
42
AN15
I
Analog input 15
CVD15
O
Touch 15
PA13
I/O
Port A digital I/O 13
43
OC4
O
Output compare 4
44
AN14
I
Analog input 14
PA14
I/O
Port A digital I/O 14
CVD14
O
Touch 4
45
PB12
I/O
Port B digital I/O 12
IRQ
O
IRQ
46
AN6
I
Analog input 6
CVD6
O
Touch 6
PB6
I/O
Port B digital I/O 6
47
OC1
O
Output compare 1
48
AN9
I
Analog input 9
CVD9
O
Touch 9
PB9
I/O
Port B digital I/O 9
49
AN7
I
Analog input 7
PB7
I/O
Port B digital I/O 7
CVD7
O
Touch 7
50
VDD
P
Input supply voltage (3.3V)
51
VDD
P
Input supply voltage (3.3V)
52
AN5
I
Analog input 5
CVD5
O
Touch 5
PB5
I/O
Port B digital I/O 5
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