18.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below).

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 18-1. PPS Input Selection Table
PeripheralPPS Input RegisterDefault Pin Selection at PORRegister Reset Value at PORAvailable Input Port
28-Pin Devices40-Pin Devices
External Interrupt INTPPSRB0‘b001 000ABAB
Timer0 ClockT0CKIPPSRA4‘b000 100ABAB
Timer1 ClockT1CKIPPSRC0‘b010 000ACAC
Timer1 GateT1GPPSRB5‘b001 101BCBC
Timer3 ClockT3CKIPPSRC0‘b010 000BCBC
Timer3 GateT3GPPSRC0‘b010 000ACAC
Timer2 InputT2INPPSRC3‘b010 011ACAC
Timer4 InputT4INPPSRC5‘b010 101BCBC
Timer6 InputT6INPPSRB7‘b001 111BCBD
CCP1CCP1PPSRC2‘b010 010BCBC
CCP2CCP2PPSRC1‘b010 001BCBC
CWG1CWG1PPSRB0‘b001 000BCBD
CLCIN0CLCIN0PPSRA0‘b000 000ACAC
CLCIN1CLCIN1PPSRA1‘b000 001ACAC
CLCIN2CLCIN2PPSRB6‘b001 110BCBD
CLCIN3CLCIN3PPSRB7‘b001 111BCBD
SCL1/SCK1SSP1CLKPPS(1)RC3‘b010 011BCBC
SDA1/SDI1SSP1DATPPS(1)RC4‘b010 100BCBC
SS1SSP1SSPPSRA5‘b000 101ACAD
SCL2/SCK2SSP2CLKPPS(1)RB1‘b001 001BCBD
SDA2/SDI2SSP2DATPPS(1)RB2‘b001 010BCBD
SS2SSP2SSPPSRB0‘b001 000BCBD
RX1/DT1RX1PPSRC7‘b010 111BCBC
CK1CK1PPSRC6‘b010 110BCBC
RX2/DT2RX2PPSRB7‘b001 111BCBD
CK2CK2PPSRB6‘b001 110BCBD
ADC Conversion TriggerADACTPPSRB4‘b001 100BCBD
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.